From 5efbb4442a0e8c653539e263bf87c48849280e23 Mon Sep 17 00:00:00 2001 From: Alexandru Date: Thu, 28 Aug 2014 10:11:44 -0500 Subject: mem: adding architectural page table support for SE mode This patch enables the use of page tables that are stored in system memory and respect x86 specification, in SE mode. It defines an architectural page table for x86 as a MultiLevelPageTable class and puts a placeholder class for other ISAs page tables, giving the possibility for future implementation. --- src/arch/x86/process.hh | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/arch/x86/process.hh') diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh index 6a221e792..2fb051953 100644 --- a/src/arch/x86/process.hh +++ b/src/arch/x86/process.hh @@ -44,6 +44,7 @@ #include #include "sim/process.hh" +#include "mem/multi_level_page_table.hh" class SyscallDesc; @@ -133,6 +134,14 @@ namespace X86ISA X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width); void setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val); }; + + /** + * Declaration of architectural page table for x86. + * + * These page tables are stored in system memory and respect x86 specification. + */ + typedef MultiLevelPageTable ArchPageTable; + } #endif // __ARCH_X86_PROCESS_HH__ -- cgit v1.2.3