From c55a467a06eaa59c47c52a2adddc266b8e545589 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Sun, 2 Nov 2008 21:56:57 -0500 Subject: make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. --- src/arch/x86/tlb.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/x86/tlb.cc') diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 5db678919..17374fa0c 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -654,7 +654,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) */ // Force the access to be uncacheable. req->setFlags(req->getFlags() | UNCACHEABLE); - req->setPaddr(x86LocalAPICAddress(tc->readCpuId(), paddr - baseAddr)); + req->setPaddr(x86LocalAPICAddress(tc->cpuId(), paddr - baseAddr)); } #endif return NoFault; -- cgit v1.2.3