From 504f90f76350ce14debfbfa837423144b0abdbe4 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 2 Oct 2007 23:00:37 -0700 Subject: X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging. --HG-- extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af --- src/arch/x86/tlb.hh | 133 +++++++++++++++++++++------------------------------- 1 file changed, 53 insertions(+), 80 deletions(-) (limited to 'src/arch/x86/tlb.hh') diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 24373c623..720b03b98 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -58,11 +58,11 @@ #ifndef __ARCH_X86_TLB_HH__ #define __ARCH_X86_TLB_HH__ -#include "config/full_system.hh" - -#if FULL_SYSTEM +#include -#include "arch/segmentregs.hh" +#include "arch/x86/pagetable.hh" +#include "arch/x86/segmentregs.hh" +#include "config/full_system.hh" #include "mem/request.hh" #include "params/X86DTB.hh" #include "params/X86ITB.hh" @@ -76,102 +76,75 @@ namespace X86ISA { static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; - struct TlbEntry - { - Addr pageStart; - TlbEntry() {} - TlbEntry(Addr paddr) : pageStart(paddr) {} - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - }; - -class TLB : public SimObject -{ - public: - typedef X86TLBParams Params; - TLB(const Params *p); - - void dumpAll(); - - // Checkpointing - virtual void serialize(std::ostream &os); - virtual void unserialize(Checkpoint *cp, const std::string §ion); -}; - -class ITB : public TLB -{ - public: - typedef X86ITBParams Params; - ITB(const Params *p) : TLB(p) - { - } - - Fault translate(RequestPtr &req, ThreadContext *tc); - - friend class DTB; -}; - -class DTB : public TLB -{ - public: - typedef X86DTBParams Params; - DTB(const Params *p) : TLB(p) + class TLB : public SimObject { - } - - Fault translate(RequestPtr &req, ThreadContext *tc, bool write); -#if FULL_SYSTEM - Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); - Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); +#if !FULL_SYSTEM + protected: + friend class FakeITLBFault; + friend class FakeDTLBFault; #endif + public: + typedef X86TLBParams Params; + TLB(const Params *p); - // Checkpointing - virtual void serialize(std::ostream &os); - virtual void unserialize(Checkpoint *cp, const std::string §ion); -}; + void dumpAll(); -} + TlbEntry *lookup(Addr va, bool update_lru = true); -#else + protected: + int size; -#include + TlbEntry * tlb; -#include "arch/x86/segmentregs.hh" -#include "sim/host.hh" -#include "sim/tlb.hh" + typedef std::list EntryList; + EntryList freeList; + EntryList entryList; -class Checkpoint; + void insert(Addr vpn, TlbEntry &entry); -namespace X86ISA -{ - static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; + void invalidateAll(); - struct TlbEntry - { - Addr pageStart; - TlbEntry() {} - TlbEntry(Addr paddr) : pageStart(paddr) {} + void invalidateNonGlobal(); - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); + void demapPage(Addr va); + + public: + // Checkpointing + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); }; - class ITB : public GenericTLB + class ITB : public TLB { public: - ITB(const Params *p) : GenericTLB(p) - {} + typedef X86ITBParams Params; + ITB(const Params *p) : TLB(p) + { + } + + Fault translate(RequestPtr &req, ThreadContext *tc); + + friend class DTB; }; - class DTB : public GenericTLB + class DTB : public TLB { public: - DTB(const Params *p) : GenericTLB(p) - {} - }; -}; + typedef X86DTBParams Params; + DTB(const Params *p) : TLB(p) + { + } + Fault translate(RequestPtr &req, ThreadContext *tc, bool write); +#if FULL_SYSTEM + Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); + Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); #endif + // Checkpointing + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); + }; +} + #endif // __ARCH_X86_TLB_HH__ -- cgit v1.2.3