From 550c31849024a2184887df87aae39617ebfe0d6a Mon Sep 17 00:00:00 2001
From: Andreas Sandberg <Andreas.Sandberg@ARM.com>
Date: Wed, 11 Feb 2015 10:23:27 -0500
Subject: sim: Move the BaseTLB to src/arch/generic/

The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.

--HG--
rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py
rename : src/sim/tlb.cc => src/arch/generic/tlb.cc
rename : src/sim/tlb.hh => src/arch/generic/tlb.hh
---
 src/arch/x86/tlb.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/arch/x86/tlb.hh')

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index e1089f90c..77f9fc49d 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -44,6 +44,7 @@
 #include <string>
 #include <vector>
 
+#include "arch/generic/tlb.hh"
 #include "arch/x86/regs/segment.hh"
 #include "arch/x86/pagetable.hh"
 #include "base/trie.hh"
@@ -51,7 +52,6 @@
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
 #include "sim/sim_object.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 class Packet;
-- 
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