From 6ed47e94644f854baa33d1e9f367cc9eebd99abf Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:16:15 -0800
Subject: CPU: Implement translateTiming which defers to translateAtomic, and
 convert the timing simple CPU to use it.

---
 src/arch/x86/tlb.hh | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

(limited to 'src/arch/x86/tlb.hh')

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 91bb4a761..56730983a 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -138,8 +138,10 @@ namespace X86ISA
         EntryList entryList;
 
         template<class TlbFault>
-        Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
+        Fault translateAtomic(RequestPtr req, ThreadContext *tc,
                 bool write, bool execute);
+        void translateTiming(RequestPtr req, ThreadContext *tc,
+                Translation *translation, bool write, bool execute);
 
       public:
 
@@ -159,7 +161,9 @@ namespace X86ISA
             _allowNX = false;
         }
 
-        Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+        Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+        void translateTiming(RequestPtr req, ThreadContext *tc,
+                Translation *translation);
 
         friend class DTB;
     };
@@ -172,7 +176,9 @@ namespace X86ISA
         {
             _allowNX = true;
         }
-        Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
+        Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
+        void translateTiming(RequestPtr req, ThreadContext *tc,
+                Translation *translation, bool write);
 #if FULL_SYSTEM
         Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
         Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-- 
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