From c305e150048b2ac92891b1054f0c65a6c3374e90 Mon Sep 17 00:00:00 2001 From: Swapnil Haria Date: Tue, 13 Jun 2017 09:46:58 -0500 Subject: x86: Add stats to X86 TLB Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4 Signed-off-by: Sean Wilson Reviewed-on: https://gem5-review.googlesource.com/3980 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/arch/x86/tlb.hh | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/arch/x86/tlb.hh') diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index a134ad427..09cd6edc7 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -100,6 +100,12 @@ namespace X86ISA TlbEntryTrie trie; uint64_t lruSeq; + // Statistics + Stats::Scalar rdAccesses; + Stats::Scalar wrAccesses; + Stats::Scalar rdMisses; + Stats::Scalar wrMisses; + Fault translateInt(RequestPtr req, ThreadContext *tc); Fault translate(RequestPtr req, ThreadContext *tc, @@ -142,6 +148,11 @@ namespace X86ISA TlbEntry * insert(Addr vpn, TlbEntry &entry); + /* + * Function to register Stats + */ + void regStats(); + // Checkpointing void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; -- cgit v1.2.3