From dc6f96017135da7f3beae5055195de3cf8e47c6c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 1 Dec 2007 23:03:39 -0800 Subject: X86: Reorganize segmentation and implement segment selector movs. --HG-- extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8 --- src/arch/x86/utility.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/arch/x86/utility.cc') diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index 69179c1f4..f45d9083b 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -143,16 +143,16 @@ void initCPU(ThreadContext *tc, int cpuId) tc->readMiscReg(MISCREG_CS_BASE)); tc->setNextPC(tc->readPC() + sizeof(MachInst)); - tc->setMiscReg(MISCREG_GDTR_BASE, 0); - tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff); + tc->setMiscReg(MISCREG_TSG_BASE, 0); + tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); tc->setMiscReg(MISCREG_IDTR_BASE, 0); tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); - tc->setMiscReg(MISCREG_LDTR, 0); - tc->setMiscReg(MISCREG_LDTR_BASE, 0); - tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff); - tc->setMiscReg(MISCREG_LDTR_ATTR, 0); + tc->setMiscReg(MISCREG_TSL, 0); + tc->setMiscReg(MISCREG_TSL_BASE, 0); + tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff); + tc->setMiscReg(MISCREG_TSL_ATTR, 0); tc->setMiscReg(MISCREG_TR, 0); tc->setMiscReg(MISCREG_TR_BASE, 0); @@ -306,8 +306,8 @@ void startupCPU(ThreadContext *tc, int cpuId) uint64_t csDescVal = csDesc; physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8); - tc->setMiscReg(MISCREG_GDTR_BASE, GDTBase); - tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xF); + tc->setMiscReg(MISCREG_TSG_BASE, GDTBase); + tc->setMiscReg(MISCREG_TSG_LIMIT, 0xF); /* * Identity map the first 4GB of memory. In order to map this region -- cgit v1.2.3