From 247586274724ea9f2a22a87747c9e074870d16a8 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Thu, 16 Oct 2014 05:49:44 -0400
Subject: arch,x86,mem: Dynamically determine the ISA for Ruby store check

This patch makes the memory system ISA-agnostic by enabling the Ruby
Sequencer to dynamically determine if it has to do a store check. To
enable this check, the ISA is encoded as an enum, and the system
is able to provide the ISA to the Sequencer at run time.

--HG--
rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh
---
 src/arch/x86/insts/microldstop.hh |  9 +-----
 src/arch/x86/ldstflags.hh         | 60 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+), 8 deletions(-)
 create mode 100644 src/arch/x86/ldstflags.hh

(limited to 'src/arch/x86')

diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index 4d96c0ec0..32f3fec04 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -41,20 +41,13 @@
 #define __ARCH_X86_INSTS_MICROLDSTOP_HH__
 
 #include "arch/x86/insts/microop.hh"
+#include "arch/x86/ldstflags.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
 #include "sim/faults.hh"
 
 namespace X86ISA
 {
-    const Request::FlagsType SegmentFlagMask = mask(4);
-    const int FlagShift = 4;
-    enum FlagBit {
-        CPL0FlagBit = 1,
-        AddrSizeFlagBit = 2,
-        StoreCheck = 4
-    };
-
     /**
      * Base class for load and store ops
      */
diff --git a/src/arch/x86/ldstflags.hh b/src/arch/x86/ldstflags.hh
new file mode 100644
index 000000000..ce86bde4c
--- /dev/null
+++ b/src/arch/x86/ldstflags.hh
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_LDSTFLAGS_HH__
+#define __ARCH_X86_LDSTFLAGS_HH__
+
+#include "base/bitfield.hh"
+#include "mem/request.hh"
+
+/**
+ * This is exposed globally, independent of the ISA.
+ */
+namespace X86ISA
+{
+    const Request::FlagsType M5_VAR_USED SegmentFlagMask = mask(4);
+    const int FlagShift = 4;
+    enum FlagBit {
+        CPL0FlagBit = 1,
+        AddrSizeFlagBit = 2,
+        StoreCheck = 4
+    };
+}
+
+#endif //__ARCH_X86_LDSTFLAGS_HH__
-- 
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