From 2e4fb3f1390c2f6551817a99cd6e5329d6c28b25 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 1 Mar 2011 22:42:59 -0800 Subject: X86: Mark IO reads and writes as non-speculative. --- .../general_purpose/input_output/general_io.py | 12 +++++--- .../general_purpose/input_output/string_io.py | 12 +++++--- src/arch/x86/isa/microops/ldstop.isa | 34 +++++++++++++--------- 3 files changed, 37 insertions(+), 21 deletions(-) (limited to 'src/arch/x86') diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py index 0674f0361..c034f8a48 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -42,22 +42,26 @@ microcode = ''' def macroop IN_R_I { .adjust_imm trimImm(8) limm t1, imm, dataSize=asz - ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8 + ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True }; def macroop IN_R_R { zexti t2, regm, 15, dataSize=8 - ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True }; def macroop OUT_I_R { .adjust_imm trimImm(8) limm t1, imm, dataSize=8 - st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8 + st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True }; def macroop OUT_R_R { zexti t2, reg, 15, dataSize=8 - st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py index fee7b6599..3c90ee7e7 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py @@ -45,7 +45,8 @@ def macroop INS_M_R { zexti t2, reg, 15, dataSize=8 - ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True st t6, es, [1, t0, rdi] add rdi, rdi, t3, dataSize=asz @@ -63,7 +64,8 @@ def macroop INS_E_M_R { zexti t2, reg, 15, dataSize=8 topOfLoop: - ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True st t6, es, [1, t0, rdi] subi rcx, rcx, 1, flags=(EZF,), dataSize=asz @@ -83,7 +85,8 @@ def macroop OUTS_R_M { zexti t2, reg, 15, dataSize=8 ld t6, ds, [1, t0, rsi] - st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True add rsi, rsi, t3, dataSize=asz }; @@ -101,7 +104,8 @@ def macroop OUTS_E_R_M { topOfLoop: ld t6, ds, [1, t0, rsi] - st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True subi rcx, rcx, 1, flags=(EZF,), dataSize=asz add rsi, rsi, t3, dataSize=asz diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 86c2dccf7..245859722 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -272,7 +272,7 @@ def template MicroLdStOpConstructor {{ let {{ class LdStOp(X86Microop): def __init__(self, data, segment, addr, disp, - dataSize, addressSize, baseFlags, atCPL0, prefetch): + dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): self.data = data [self.scale, self.index, self.base] = addr self.disp = disp @@ -285,7 +285,9 @@ let {{ self.instFlags = "" if prefetch: self.memFlags += " | Request::PREFETCH" - self.instFlags += " | StaticInst::IsDataPrefetch" + self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" + if nonSpec: + self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" self.memFlags += " | (machInst.legacy.addr ? " + \ "(AddrSizeFlagBit << FlagShift) : 0)" @@ -306,7 +308,7 @@ let {{ class BigLdStOp(X86Microop): def __init__(self, data, segment, addr, disp, - dataSize, addressSize, baseFlags, atCPL0, prefetch): + dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): self.data = data [self.scale, self.index, self.base] = addr self.disp = disp @@ -316,8 +318,12 @@ let {{ self.memFlags = baseFlags if atCPL0: self.memFlags += " | (CPL0FlagBit << FlagShift)" + self.instFlags = "" if prefetch: self.memFlags += " | Request::PREFETCH" + self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" + if nonSpec: + self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" self.memFlags += " | (machInst.legacy.addr ? " + \ "(AddrSizeFlagBit << FlagShift) : 0)" @@ -335,7 +341,7 @@ let {{ ''' allocator = allocString % { "class_name" : self.className, - "flags" : self.microFlagsText(microFlags), + "flags" : self.microFlagsText(microFlags) + self.instFlags, "scale" : self.scale, "index" : self.index, "base" : self.base, "disp" : self.disp, @@ -386,10 +392,10 @@ let {{ def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize", - atCPL0=False, prefetch=False): + atCPL0=False, prefetch=False, nonSpec=False): super(LoadOp, self).__init__(data, segment, addr, disp, dataSize, addressSize, mem_flags, - atCPL0, prefetch) + atCPL0, prefetch, nonSpec) self.className = Name self.mnemonic = name @@ -430,9 +436,10 @@ let {{ def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize", - atCPL0=False): - super(StoreOp, self).__init__(data, segment, addr, - disp, dataSize, addressSize, mem_flags, atCPL0, False) + atCPL0=False, nonSpec=False): + super(StoreOp, self).__init__(data, segment, addr, disp, + dataSize, addressSize, mem_flags, atCPL0, False, + nonSpec) self.className = Name self.mnemonic = name @@ -456,8 +463,8 @@ let {{ class LeaOp(LdStOp): def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize"): - super(LeaOp, self).__init__(data, segment, - addr, disp, dataSize, addressSize, "0", False, False) + super(LeaOp, self).__init__(data, segment, addr, disp, + dataSize, addressSize, "0", False, False, False) self.className = "Lea" self.mnemonic = "lea" @@ -476,7 +483,8 @@ let {{ dataSize="env.dataSize", addressSize="env.addressSize"): super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, - addr, disp, dataSize, addressSize, "0", False, False) + addr, disp, dataSize, addressSize, "0", False, False, + False) self.className = "Tia" self.mnemonic = "tia" @@ -488,7 +496,7 @@ let {{ addressSize="env.addressSize", atCPL0=False): super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, addr, disp, dataSize, addressSize, "Request::NO_ACCESS", - atCPL0, False) + atCPL0, False, False) self.className = "Cda" self.mnemonic = "cda" -- cgit v1.2.3