From 5592798865ece858bab2b444bc782d19121e2566 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 6 Feb 2016 17:21:19 -0800 Subject: style: fix missing spaces in control statements Result of running 'hg m5style --skip-all --fix-control -a'. --- src/arch/x86/bios/intelmp.cc | 2 +- src/arch/x86/cpuid.cc | 2 +- src/arch/x86/decoder.cc | 18 +++++++++--------- src/arch/x86/insts/microldstop.cc | 2 +- src/arch/x86/insts/microregop.cc | 20 ++++++++++---------- src/arch/x86/insts/static_inst.cc | 14 +++++++------- src/arch/x86/insts/static_inst.hh | 6 +++--- src/arch/x86/nativetrace.cc | 10 +++++----- src/arch/x86/pagetable_walker.cc | 4 ++-- src/arch/x86/process.cc | 6 +++--- src/arch/x86/types.hh | 26 +++++++++++++------------- 11 files changed, 55 insertions(+), 55 deletions(-) (limited to 'src/arch/x86') diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc index c907a63fe..98b3a6f08 100644 --- a/src/arch/x86/bios/intelmp.cc +++ b/src/arch/x86/bios/intelmp.cc @@ -76,7 +76,7 @@ writeOutField(PortProxy& proxy, Addr addr, T val) proxy.writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T)); uint8_t checkSum = 0; - while(guestVal) { + while (guestVal) { checkSum += guestVal; guestVal >>= 8; } diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc index 6817ca742..f1424cce4 100644 --- a/src/arch/x86/cpuid.cc +++ b/src/arch/x86/cpuid.cc @@ -142,7 +142,7 @@ namespace X86ISA { funcNum); return false; } - } else if(family == 0x0000) { + } else if (family == 0x0000) { // The standard functions switch (funcNum) { case VendorAndLargestStdFunc: diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc index fb5a4e001..38394875d 100644 --- a/src/arch/x86/decoder.cc +++ b/src/arch/x86/decoder.cc @@ -386,7 +386,7 @@ Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable, //Figure out the effective address size. This can be overriden to //a fixed value at the decoder level. int logAddrSize; - if(emi.legacy.addr) + if (emi.legacy.addr) logAddrSize = altAddr; else logAddrSize = defAddr; @@ -410,7 +410,7 @@ Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable, if (modrmTable[opcode]) { nextState = ModRMState; } else { - if(immediateSize) { + if (immediateSize) { nextState = ImmediateState; } else { instDone = true; @@ -439,7 +439,7 @@ Decoder::processExtendedOpcode(ByteTable &immTable) //Figure out the effective address size. This can be overriden to //a fixed value at the decoder level. int logAddrSize; - if(emi.legacy.addr) + if (emi.legacy.addr) logAddrSize = altAddr; else logAddrSize = defAddr; @@ -509,9 +509,9 @@ Decoder::doModRMState(uint8_t nextByte) if (modRM.rm == 4 && modRM.mod != 3) { // && in 32/64 bit mode) nextState = SIBState; - } else if(displacementSize) { + } else if (displacementSize) { nextState = DisplacementState; - } else if(immediateSize) { + } else if (immediateSize) { nextState = ImmediateState; } else { instDone = true; @@ -537,7 +537,7 @@ Decoder::doSIBState(uint8_t nextByte) displacementSize = 4; if (displacementSize) { nextState = DisplacementState; - } else if(immediateSize) { + } else if (immediateSize) { nextState = ImmediateState; } else { instDone = true; @@ -560,7 +560,7 @@ Decoder::doDisplacementState() DPRINTF(Decoder, "Collecting %d byte displacement, got %d bytes.\n", displacementSize, immediateCollected); - if(displacementSize == immediateCollected) { + if (displacementSize == immediateCollected) { //Reset this for other immediates. immediateCollected = 0; //Sign extend the displacement @@ -580,7 +580,7 @@ Decoder::doDisplacementState() } DPRINTF(Decoder, "Collected displacement %#x.\n", emi.displacement); - if(immediateSize) { + if (immediateSize) { nextState = ImmediateState; } else { instDone = true; @@ -608,7 +608,7 @@ Decoder::doImmediateState() DPRINTF(Decoder, "Collecting %d byte immediate, got %d bytes.\n", immediateSize, immediateCollected); - if(immediateSize == immediateCollected) + if (immediateSize == immediateCollected) { //Reset this for other immediates. immediateCollected = 0; diff --git a/src/arch/x86/insts/microldstop.cc b/src/arch/x86/insts/microldstop.cc index 4fc0ec8e3..e98767992 100644 --- a/src/arch/x86/insts/microldstop.cc +++ b/src/arch/x86/insts/microldstop.cc @@ -49,7 +49,7 @@ namespace X86ISA std::stringstream response; printMnemonic(response, instMnem, mnemonic); - if(flags[IsLoad]) + if (flags[IsLoad]) printDestReg(response, 0, dataSize); else printSrcReg(response, 2, dataSize); diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc index f5f32e30f..b49cda376 100644 --- a/src/arch/x86/insts/microregop.cc +++ b/src/arch/x86/insts/microregop.cc @@ -52,27 +52,27 @@ namespace X86ISA { DPRINTF(X86, "flagMask = %#x\n", flagMask); uint64_t flags = oldFlags & ~flagMask; - if(flagMask & (ECFBit | CFBit)) + if (flagMask & (ECFBit | CFBit)) { - if(findCarry(dataSize*8, _dest, _src1, _src2)) + if (findCarry(dataSize*8, _dest, _src1, _src2)) flags |= (flagMask & (ECFBit | CFBit)); - if(subtract) + if (subtract) flags ^= (flagMask & (ECFBit | CFBit)); } - if(flagMask & PFBit && !findParity(8, _dest)) + if (flagMask & PFBit && !findParity(8, _dest)) flags |= PFBit; - if(flagMask & AFBit) + if (flagMask & AFBit) { - if(findCarry(4, _dest, _src1, _src2)) + if (findCarry(4, _dest, _src1, _src2)) flags |= AFBit; - if(subtract) + if (subtract) flags ^= AFBit; } - if(flagMask & (EZFBit | ZFBit) && findZero(dataSize*8, _dest)) + if (flagMask & (EZFBit | ZFBit) && findZero(dataSize*8, _dest)) flags |= (flagMask & (EZFBit | ZFBit)); - if(flagMask & SFBit && findNegative(dataSize*8, _dest)) + if (flagMask & SFBit && findNegative(dataSize*8, _dest)) flags |= SFBit; - if(flagMask & OFBit && findOverflow(dataSize*8, _dest, _src1, _src2)) + if (flagMask & OFBit && findOverflow(dataSize*8, _dest, _src1, _src2)) flags |= OFBit; return flags; } diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc index 39091289f..709e0a610 100644 --- a/src/arch/x86/insts/static_inst.cc +++ b/src/arch/x86/insts/static_inst.cc @@ -107,14 +107,14 @@ namespace X86ISA void X86StaticInst::printSrcReg(std::ostream &os, int reg, int size) const { - if(_numSrcRegs > reg) + if (_numSrcRegs > reg) printReg(os, _srcRegIdx[reg], size); } void X86StaticInst::printDestReg(std::ostream &os, int reg, int size) const { - if(_numDestRegs > reg) + if (_numDestRegs > reg) printReg(os, _destRegIdx[reg], size); } @@ -139,9 +139,9 @@ namespace X86ISA bool fold = rel_reg & IntFoldBit; rel_reg &= ~IntFoldBit; - if(fold) + if (fold) suffix = "h"; - else if(rel_reg < 8 && size == 1) + else if (rel_reg < 8 && size == 1) suffix = "l"; switch (rel_reg) { @@ -247,14 +247,14 @@ namespace X86ISA } else { if (scale != 0 && index != ZeroReg) { - if(scale != 1) + if (scale != 1) ccprintf(os, "%d*", scale); printReg(os, index, addressSize); someAddr = true; } if (base != ZeroReg) { - if(someAddr) + if (someAddr) os << " + "; printReg(os, base, addressSize); someAddr = true; @@ -262,7 +262,7 @@ namespace X86ISA } if (disp != 0) { - if(someAddr) + if (someAddr) os << " + "; ccprintf(os, "%#x", disp); someAddr = true; diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh index b4e348fd9..d06470a3e 100644 --- a/src/arch/x86/insts/static_inst.hh +++ b/src/arch/x86/insts/static_inst.hh @@ -91,7 +91,7 @@ namespace X86ISA inline uint64_t merge(uint64_t into, uint64_t val, int size) const { X86IntReg reg = into; - if(_destRegIdx[0] & IntFoldBit) + if (_destRegIdx[0] & IntFoldBit) { reg.H = val; return reg; @@ -122,7 +122,7 @@ namespace X86ISA { X86IntReg reg = from; DPRINTF(X86, "Picking with size %d\n", size); - if(_srcRegIdx[idx] & IntFoldBit) + if (_srcRegIdx[idx] & IntFoldBit) return reg.H; switch(size) { @@ -143,7 +143,7 @@ namespace X86ISA { X86IntReg reg = from; DPRINTF(X86, "Picking with size %d\n", size); - if(_srcRegIdx[idx] & IntFoldBit) + if (_srcRegIdx[idx] & IntFoldBit) return reg.SH; switch(size) { diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc index b7d903a1b..d8b3564a3 100644 --- a/src/arch/x86/nativetrace.cc +++ b/src/arch/x86/nativetrace.cc @@ -105,9 +105,9 @@ X86NativeTrace::X86NativeTrace(const Params *p) bool X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal) { - if(!checkRcx) + if (!checkRcx) checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal); - if(checkRcx) + if (checkRcx) return checkReg(name, mVal, nVal); return true; } @@ -115,9 +115,9 @@ X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal) bool X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal) { - if(!checkR11) + if (!checkR11) checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val); - if(checkR11) + if (checkR11) return checkReg(name, mVal, nVal); return true; } @@ -142,7 +142,7 @@ X86NativeTrace::check(NativeTraceRecord *record) nState.update(this); mState.update(record->getThread()); - if(record->getStaticInst()->isSyscall()) + if (record->getStaticInst()->isSyscall()) { checkRcx = false; checkR11 = false; diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index 5c9ab6beb..5545bfa64 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -239,7 +239,7 @@ Walker::WalkerState::startWalk() nextState = Ready; if (write) walker->port.sendAtomic(write); - } while(read); + } while (read); state = Ready; nextState = Waiting; } @@ -263,7 +263,7 @@ Walker::WalkerState::startFunctional(Addr &addr, unsigned &logBytes) assert(fault == NoFault || read == NULL); state = nextState; nextState = Ready; - } while(read); + } while (read); logBytes = entry.logBytes; addr = entry.paddr; diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 0e3cff937..8d1e1da96 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -552,7 +552,7 @@ X86_64LiveProcess::initState() dataAttr.system = 1; //Initialize the segment registers. - for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) { + for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); @@ -663,7 +663,7 @@ I386LiveProcess::initState() dataAttr.system = 1; //Initialize the segment registers. - for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) { + for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); @@ -735,7 +735,7 @@ X86LiveProcess::argsInit(int pageSize, std::vector auxv = extraAuxvs; string filename; - if(argv.size() < 1) + if (argv.size() < 1) filename = ""; else filename = argv[0]; diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 99e2c826c..6451056ee 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -258,31 +258,31 @@ namespace X86ISA inline static bool operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) { - if(emi1.legacy != emi2.legacy) + if (emi1.legacy != emi2.legacy) return false; - if(emi1.rex != emi2.rex) + if (emi1.rex != emi2.rex) return false; - if(emi1.opcode.type != emi2.opcode.type) + if (emi1.opcode.type != emi2.opcode.type) return false; - if(emi1.opcode.op != emi2.opcode.op) + if (emi1.opcode.op != emi2.opcode.op) return false; - if(emi1.modRM != emi2.modRM) + if (emi1.modRM != emi2.modRM) return false; - if(emi1.sib != emi2.sib) + if (emi1.sib != emi2.sib) return false; - if(emi1.immediate != emi2.immediate) + if (emi1.immediate != emi2.immediate) return false; - if(emi1.displacement != emi2.displacement) + if (emi1.displacement != emi2.displacement) return false; - if(emi1.mode != emi2.mode) + if (emi1.mode != emi2.mode) return false; - if(emi1.opSize != emi2.opSize) + if (emi1.opSize != emi2.opSize) return false; - if(emi1.addrSize != emi2.addrSize) + if (emi1.addrSize != emi2.addrSize) return false; - if(emi1.stackSize != emi2.stackSize) + if (emi1.stackSize != emi2.stackSize) return false; - if(emi1.dispSize != emi2.dispSize) + if (emi1.dispSize != emi2.dispSize) return false; return true; } -- cgit v1.2.3