From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/arch/x86/insts/static_inst.cc |  7 +++++++
 src/arch/x86/isa.hh               |  6 ++++++
 src/arch/x86/registers.hh         | 11 ++++++++++-
 src/arch/x86/utility.cc           |  4 ++++
 4 files changed, 27 insertions(+), 1 deletion(-)

(limited to 'src/arch/x86')

diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index 39091289f..49ea6ef4e 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -225,12 +225,19 @@ namespace X86ISA
             ccprintf(os, "%%cc%d", rel_reg);
             break;
 
+          case VectorRegClass:
+            ccprintf(os, "%%cc%d", rel_reg);
+            break;
+
           case MiscRegClass:
             switch (rel_reg) {
               default:
                 ccprintf(os, "%%ctrl%d", rel_reg);
             }
             break;
+
+          default:
+            panic("Invalid register class!\n");
         }
     }
 
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 88f4980ae..779241c55 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -91,6 +91,12 @@ namespace X86ISA
             return reg;
         }
 
+        int
+        flattenVectorIndex(int reg) const
+        {
+            return reg;
+        }
+
         int
         flattenMiscIndex(int reg) const
         {
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index ebd88136e..ad40fe17f 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -57,6 +57,7 @@ const int NumMiscRegs = NUM_MISCREGS;
 const int NumIntArchRegs = NUM_INTREGS;
 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
 const int NumCCRegs = NUM_CCREGS;
+const int NumVectorRegs = 0;
 
 #define ISA_HAS_CC_REGS
 
@@ -72,7 +73,8 @@ enum DependenceTags {
     // we just start at (1 << 7) == 128.
     FP_Reg_Base = 128,
     CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
-    Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
+    Vector_Reg_Base = CC_Reg_Base + NumCCRegs,
+    Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs,
     Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
 };
 
@@ -91,6 +93,13 @@ const int SyscallPseudoReturnReg = INTREG_RDX;
 
 typedef uint64_t IntReg;
 typedef uint64_t CCReg;
+
+// vector register file entry type
+typedef uint64_t VectorRegElement;
+const int NumVectorRegElements = 0;
+const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
+typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
+
 //XXX Should this be a 128 bit structure for XMM memory ops?
 typedef uint64_t LargestRead;
 typedef uint64_t MiscReg;
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index f7d0f816e..e1be61180 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -245,6 +245,10 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     //copy condition-code regs
     for (int i = 0; i < NumCCRegs; ++i)
          dest->setCCRegFlat(i, src->readCCRegFlat(i));
+
+    // copy vector regs when added to the architecture
+    assert(NumVectorRegs == 0);
+
     copyMiscRegs(src, dest);
     dest->pcState(src->pcState());
 }
-- 
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