From 94b08bed07d13106381a0bb692bf0d879c5353d4 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 9 Oct 2008 22:19:39 -0700 Subject: SimObjects: Clean up handling of C++ namespaces. Make them easier to express by only having the cxx_type parameter which has the full namespace name, and drop the cxx_namespace thing. Add support for multiple levels of namespace. --- src/arch/x86/X86TLB.py | 11 +++-------- src/arch/x86/bios/E820.py | 6 ++---- 2 files changed, 5 insertions(+), 12 deletions(-) (limited to 'src/arch/x86') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 8dd53620e..c20566efb 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -62,8 +62,7 @@ from m5 import build_env if build_env['FULL_SYSTEM']: class X86PagetableWalker(MemObject): type = 'X86PagetableWalker' - cxx_namespace = 'X86ISA' - cxx_class = 'Walker' + cxx_class = 'X86ISA::Walker' port = Port("Port for the hardware table walker") system = Param.System(Parent.any, "system object") @@ -77,14 +76,10 @@ class X86TLB(SimObject): class X86DTB(X86TLB): type = 'X86DTB' - cxx_namespace = 'X86ISA' - cxx_class = 'DTB' - + cxx_class = 'X86ISA::DTB' size = 64 class X86ITB(X86TLB): type = 'X86ITB' - cxx_namespace = 'X86ISA' - cxx_class = 'ITB' - + cxx_class = 'X86ISA::ITB' size = 64 diff --git a/src/arch/x86/bios/E820.py b/src/arch/x86/bios/E820.py index e161cd56f..288c253fb 100644 --- a/src/arch/x86/bios/E820.py +++ b/src/arch/x86/bios/E820.py @@ -58,8 +58,7 @@ from m5.SimObject import SimObject class X86E820Entry(SimObject): type = 'X86E820Entry' - cxx_namespace = 'X86ISA' - cxx_class = 'E820Entry' + cxx_class = 'X86ISA::E820Entry' addr = Param.Addr(0, 'address of the beginning of the region') size = Param.MemorySize('0B', 'size of the region') @@ -67,7 +66,6 @@ class X86E820Entry(SimObject): class X86E820Table(SimObject): type = 'X86E820Table' - cxx_namespace = 'X86ISA' - cxx_class = 'E820Table' + cxx_class = 'X86ISA::E820Table' entries = VectorParam.X86E820Entry([], 'entries for the e820 table') -- cgit v1.2.3