From fcad6e3b13410ab6c7263ce42b5e657c16f79e1d Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:17:38 -0800
Subject: X86: Add a wrattr microop.

---
 src/arch/x86/isa/microops/regop.isa | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/arch/x86')

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index f21621e30..4434f9e74 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1009,6 +1009,11 @@ let {{
             SegSelDest = psrc1;
         '''
 
+    class WrAttr(SegOp):
+        code = '''
+            SegAttrDest = psrc1;
+        '''
+
     class Rdbase(SegOp):
         code = '''
             DestReg = SegBaseSrc1;
-- 
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