From fddfa71658a35f91c249ce0b7b67984d979a4fb4 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 25 Oct 2007 19:04:44 -0700
Subject: TLB: Fix serialization issues with the tlb entries and make the page
 table store the process, not the system.

--HG--
extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8
---
 src/arch/x86/faults.cc    | 28 +++++-----------------------
 src/arch/x86/pagetable.cc |  6 ++++++
 src/arch/x86/pagetable.hh | 22 ++++++++++++++--------
 src/arch/x86/tlb.cc       |  2 +-
 4 files changed, 26 insertions(+), 32 deletions(-)

(limited to 'src/arch/x86')

diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 69cbadc93..b9cac0297 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -118,20 +118,11 @@ namespace X86ISA
         DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n",
                 vaddr, tc->readPC());
         Process *p = tc->getProcessPtr();
-        Addr paddr;
-        bool success = p->pTable->translate(vaddr, paddr);
+        TlbEntry entry;
+        bool success = p->pTable->lookup(vaddr, entry);
         if(!success) {
             panic("Tried to execute unmapped address %#x.\n", vaddr);
         } else {
-            TlbEntry entry;
-            entry.pageStart = p->pTable->pageAlign(paddr);
-            entry.writeable = false;
-            entry.user = true;
-            entry.uncacheable = false;
-            entry.global = false;
-            entry.patBit = 0;
-            entry.noExec = false;
-            entry.size = PageBytes;
             Addr alignedVaddr = p->pTable->pageAlign(vaddr);
             DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
             tc->getITBPtr()->insert(alignedVaddr, entry);
@@ -143,24 +134,15 @@ namespace X86ISA
         DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n",
                 vaddr, tc->readPC());
         Process *p = tc->getProcessPtr();
-        Addr paddr;
-        bool success = p->pTable->translate(vaddr, paddr);
+        TlbEntry entry;
+        bool success = p->pTable->lookup(vaddr, entry);
         if(!success) {
             p->checkAndAllocNextPage(vaddr);
-            success = p->pTable->translate(vaddr, paddr);
+            success = p->pTable->lookup(vaddr, entry);
         }
         if(!success) {
             panic("Tried to access unmapped address %#x.\n", vaddr);
         } else {
-            TlbEntry entry;
-            entry.pageStart = p->pTable->pageAlign(paddr);
-            entry.writeable = true;
-            entry.user = true;
-            entry.uncacheable = false;
-            entry.global = false;
-            entry.patBit = 0;
-            entry.noExec = true;
-            entry.size = PageBytes;
             Addr alignedVaddr = p->pTable->pageAlign(vaddr);
             DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
             tc->getDTBPtr()->insert(alignedVaddr, entry);
diff --git a/src/arch/x86/pagetable.cc b/src/arch/x86/pagetable.cc
index 49aaab068..e16d6e659 100644
--- a/src/arch/x86/pagetable.cc
+++ b/src/arch/x86/pagetable.cc
@@ -55,12 +55,18 @@
  * Authors: Gabe Black
  */
 
+#include "arch/x86/isa_traits.hh"
 #include "arch/x86/pagetable.hh"
 #include "sim/serialize.hh"
 
 namespace X86ISA
 {
 
+TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr) :
+    paddr(_paddr), vaddr(_vaddr), size(PageBytes), writable(true), user(true),
+    uncacheable(false), global(false), patBit(0), noExec(false)
+{}
+
 void
 TlbEntry::serialize(std::ostream &os)
 {
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index aaf82ed70..cc614168c 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -76,10 +76,16 @@ namespace X86ISA
     struct TlbEntry
     {
         // The base of the physical page.
-        Addr pageStart;
+        Addr paddr;
+
+        // The beginning of the virtual page this entry maps.
+        Addr vaddr;
+        // The size of the page this entry represents.
+        Addr size;
+
         // Read permission is always available, assuming it isn't blocked by
         // other mechanisms.
-        bool writeable;
+        bool writable;
         // Whether this page is accesible without being in supervisor mode.
         bool user;
         // Whether to use write through or write back. M5 ignores this and
@@ -94,13 +100,13 @@ namespace X86ISA
         // Whether or not memory on this page can be executed.
         bool noExec;
 
-        // The beginning of the virtual page this entry maps.
-        Addr vaddr;
-        // The size of the page this entry represents.
-        Addr size;
-
+        TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
         TlbEntry() {}
-        TlbEntry(Addr paddr) : pageStart(paddr) {}
+
+        Addr pageStart()
+        {
+            return paddr;
+        }
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index d55f04080..6afee6d72 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -494,7 +494,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
 #endif
             } else {
                 // Do paging protection checks.
-                Addr paddr = entry->pageStart | (vaddr & mask(12));
+                Addr paddr = entry->paddr | (vaddr & mask(12));
                 req->setPaddr(paddr);
             }
         } else {
-- 
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