From 04300e33d49e5697565eb39956849a18ad74ea45 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:01 -0500 Subject: ARM: Remove the special naming for the new memory instructions. These are the only memory instructions now. --- src/arch/arm/insts/mem.cc | 2 +- src/arch/arm/insts/mem.hh | 80 +++++++++++++++++++++--------------------- src/arch/arm/isa/insts/ldr.isa | 16 ++++----- src/arch/arm/isa/insts/mem.isa | 10 +++--- src/arch/arm/isa/insts/str.isa | 16 ++++----- 5 files changed, 62 insertions(+), 62 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 4d56b80f8..ea98771e0 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -47,7 +47,7 @@ namespace ArmISA { void -MemoryNew::printInst(std::ostream &os, AddrMode addrMode) const +Memory::printInst(std::ostream &os, AddrMode addrMode) const { printMnemonic(os); printReg(os, dest); diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh index dd6526fe1..e58005883 100644 --- a/src/arch/arm/insts/mem.hh +++ b/src/arch/arm/insts/mem.hh @@ -47,7 +47,7 @@ namespace ArmISA { -class MemoryNew : public PredOp +class Memory : public PredOp { public: enum AddrMode { @@ -62,8 +62,8 @@ class MemoryNew : public PredOp IntRegIndex base; bool add; - MemoryNew(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - IntRegIndex _dest, IntRegIndex _base, bool _add) + Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _base, bool _add) : PredOp(mnem, _machInst, __opClass), dest(_dest), base(_base), add(_add) {} @@ -76,14 +76,14 @@ class MemoryNew : public PredOp }; // The address is a base register plus an immediate. -class MemoryNewImm : public MemoryNew +class MemoryImm : public Memory { protected: int32_t imm; - MemoryNewImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm) - : MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm) + MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm) + : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm) {} void @@ -97,18 +97,18 @@ class MemoryNewImm : public MemoryNew }; // The address is a shifted register plus an immediate -class MemoryNewReg : public MemoryNew +class MemoryReg : public Memory { protected: int32_t shiftAmt; ArmShiftType shiftType; IntRegIndex index; - MemoryNewReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - IntRegIndex _dest, IntRegIndex _base, bool _add, - int32_t _shiftAmt, ArmShiftType _shiftType, - IntRegIndex _index) - : MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add), + MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _base, bool _add, + int32_t _shiftAmt, ArmShiftType _shiftType, + IntRegIndex _index) + : Memory(mnem, _machInst, __opClass, _dest, _base, _add), shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index) {} @@ -150,19 +150,19 @@ class MemoryNewReg : public MemoryNew }; template -class MemoryNewOffset : public Base +class MemoryOffset : public Base { protected: - MemoryNewOffset(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, - bool _add, int32_t _imm) + MemoryOffset(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, + bool _add, int32_t _imm) : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) {} - MemoryNewOffset(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, - bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, - IntRegIndex _index) + MemoryOffset(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, + bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, + IntRegIndex _index) : Base(mnem, _machInst, __opClass, _dest, _base, _add, _shiftAmt, _shiftType, _index) {} @@ -171,25 +171,25 @@ class MemoryNewOffset : public Base generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - this->printInst(ss, MemoryNew::AddrMd_Offset); + this->printInst(ss, Memory::AddrMd_Offset); return ss.str(); } }; template -class MemoryNewPreIndex : public Base +class MemoryPreIndex : public Base { protected: - MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, - bool _add, int32_t _imm) + MemoryPreIndex(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, + bool _add, int32_t _imm) : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) {} - MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, - bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, - IntRegIndex _index) + MemoryPreIndex(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, + bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, + IntRegIndex _index) : Base(mnem, _machInst, __opClass, _dest, _base, _add, _shiftAmt, _shiftType, _index) {} @@ -198,25 +198,25 @@ class MemoryNewPreIndex : public Base generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - this->printInst(ss, MemoryNew::AddrMd_PreIndex); + this->printInst(ss, Memory::AddrMd_PreIndex); return ss.str(); } }; template -class MemoryNewPostIndex : public Base +class MemoryPostIndex : public Base { protected: - MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, - bool _add, int32_t _imm) + MemoryPostIndex(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, + bool _add, int32_t _imm) : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) {} - MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, - bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, - IntRegIndex _index) + MemoryPostIndex(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, + bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, + IntRegIndex _index) : Base(mnem, _machInst, __opClass, _dest, _base, _add, _shiftAmt, _shiftType, _index) {} @@ -225,7 +225,7 @@ class MemoryNewPostIndex : public Base generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - this->printInst(ss, MemoryNew::AddrMd_PostIndex); + this->printInst(ss, Memory::AddrMd_PostIndex); return ss.str(); } }; diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 259a46fd9..86cb76383 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -64,10 +64,10 @@ let {{ (newHeader, newDecoder, - newExec) = newLoadStoreBase(name, Name, imm, - eaCode, accCode, - memFlags, instFlags, - base, execTemplateBase = 'Load') + newExec) = loadStoreBase(name, Name, imm, + eaCode, accCode, + memFlags, instFlags, + base, execTemplateBase = 'Load') header_output += newHeader decoder_output += newDecoder @@ -93,7 +93,7 @@ let {{ accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size) if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewImm", post, writeback) + base = buildMemBase("MemoryImm", post, writeback) emitLoad(name, Name, True, eaCode, accCode, [], [], base) @@ -118,7 +118,7 @@ let {{ accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size) if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewReg", post, writeback) + base = buildMemBase("MemoryReg", post, writeback) emitLoad(name, Name, False, eaCode, accCode, [], [], base) @@ -143,7 +143,7 @@ let {{ ''' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewImm", post, writeback) + base = buildMemBase("MemoryImm", post, writeback) emitLoad(name, Name, True, eaCode, accCode, [], [], base) @@ -169,7 +169,7 @@ let {{ ''' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewReg", post, writeback) + base = buildMemBase("MemoryReg", post, writeback) emitLoad(name, Name, False, eaCode, accCode, [], [], base) diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index 698f95adb..a7aa0b2ed 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -38,8 +38,8 @@ // Authors: Gabe Black let {{ - def newLoadStoreBase(name, Name, imm, eaCode, accCode, memFlags, - instFlags, base = 'MemoryNew', execTemplateBase = ''): + def loadStoreBase(name, Name, imm, eaCode, accCode, memFlags, + instFlags, base = 'Memory', execTemplateBase = ''): # Make sure flags are in lists (convert to lists if not). memFlags = makeList(memFlags) instFlags = makeList(instFlags) @@ -131,11 +131,11 @@ let {{ def buildMemBase(base, post, writeback): if post and writeback: - base = "MemoryNewPostIndex<%s>" % base + base = "MemoryPostIndex<%s>" % base elif not post and writeback: - base = "MemoryNewPreIndex<%s>" % base + base = "MemoryPreIndex<%s>" % base elif not post and not writeback: - base = "MemoryNewOffset<%s>" % base + base = "MemoryOffset<%s>" % base else: raise Exception, "Illegal combination of post and writeback" return base diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index e72ca6e41..3349ba029 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -66,10 +66,10 @@ let {{ (newHeader, newDecoder, - newExec) = newLoadStoreBase(name, Name, imm, - eaCode, accCode, - memFlags, instFlags, - base, execTemplateBase = 'Store') + newExec) = loadStoreBase(name, Name, imm, + eaCode, accCode, + memFlags, instFlags, + base, execTemplateBase = 'Store') header_output += newHeader decoder_output += newDecoder @@ -95,7 +95,7 @@ let {{ accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewImm", post, writeback) + base = buildMemBase("MemoryImm", post, writeback) emitStore(name, Name, True, eaCode, accCode, [], [], base) @@ -120,7 +120,7 @@ let {{ accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewReg", post, writeback) + base = buildMemBase("MemoryReg", post, writeback) emitStore(name, Name, False, eaCode, accCode, [], [], base) @@ -142,7 +142,7 @@ let {{ accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewImm", post, writeback) + base = buildMemBase("MemoryImm", post, writeback) emitStore(name, Name, True, eaCode, accCode, [], [], base) @@ -165,7 +165,7 @@ let {{ accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewReg", post, writeback) + base = buildMemBase("MemoryReg", post, writeback) emitStore(name, Name, False, eaCode, accCode, [], [], base) -- cgit v1.2.3