From 08187e3916fa615444ed61d739ac91e284735a66 Mon Sep 17 00:00:00 2001 From: Matt Horsnell Date: Thu, 1 Mar 2012 17:26:31 -0600 Subject: ARM: Add limited CP14 support. New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available. --- src/arch/arm/isa.cc | 21 ++++++++--- src/arch/arm/isa/decoder/arm.isa | 3 +- src/arch/arm/isa/decoder/thumb.isa | 4 +- src/arch/arm/isa/formats/misc.isa | 45 ++++++++++++++++++++++- src/arch/arm/isa/formats/uncond.isa | 4 +- src/arch/arm/isa/insts/misc.isa | 54 ++++++++++++++++++++++++++- src/arch/arm/miscregs.cc | 32 +++++++++++++++- src/arch/arm/miscregs.hh | 73 ++++++++++++++++++++++++++++++++++++- 8 files changed, 223 insertions(+), 13 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a609b3ef9..b79b9346f 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -233,11 +233,20 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_FPSCR_EXC: return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; case MISCREG_L2CTLR: - // mostly unimplemented, just set NumCPUs field from sim and return - L2CTLR l2ctlr = 0; - // b00:1CPU to b11:4CPUs - l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; - return l2ctlr; + { + // mostly unimplemented, just set NumCPUs field from sim and return + L2CTLR l2ctlr = 0; + // b00:1CPU to b11:4CPUs + l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; + return l2ctlr; + } + case MISCREG_DBGDIDR: + /* For now just implement the version number. + * Return 0 as we don't support debug architecture yet. + */ + return 0; + case MISCREG_DBGDSCR_INT: + return 0; } return readMiscRegNoEffect(misc_reg); } diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index 9ab95b82f..4bd9d5cf4 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -114,6 +114,7 @@ format DataOp { 1: decode CPNUM { // 27-24=1110,4 ==1 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); + 0xe: McrMrc14::mcrMrc14(); 0xf: McrMrc15::mcrMrc15(); } // CPNUM (OP4 == 1) } //OPCODE_4 diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index f144e3003..f54cc728d 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -86,6 +86,7 @@ decode BIGTHUMB { 0x1: decode LTCOPROC { 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); + 0xe: McrMrc14::mcrMrc14(); 0xf: McrMrc15::mcrMrc15(); } } @@ -142,6 +143,7 @@ decode BIGTHUMB { 0x1: decode LTCOPROC { 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); + 0xe: McrMrc14::mcrMrc14(); 0xf: McrMrc15::mcrMrc15(); } } diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 54482864a..3865cffe2 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -78,6 +78,49 @@ def format ArmMsrMrs() {{ ''' }}; +let {{ + header_output = ''' + StaticInstPtr + decodeMcrMrc15(ExtMachInst machInst); + ''' + decoder_output = ''' + StaticInstPtr + decodeMcrMrc14(ExtMachInst machInst) + { + const uint32_t opc1 = bits(machInst, 23, 21); + const uint32_t crn = bits(machInst, 19, 16); + const uint32_t opc2 = bits(machInst, 7, 5); + const uint32_t crm = bits(machInst, 3, 0); + const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2); + const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); + + const bool isRead = bits(machInst, 20); + + switch (miscReg) { + case MISCREG_NOP: + return new NopInst(machInst); + case NUM_MISCREGS: + return new FailUnimplemented( + csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", + crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(), + machInst); + default: + if (isRead) { + return new Mrc14(machInst, rt, (IntRegIndex)miscReg); + } else { + return new Mcr14(machInst, (IntRegIndex)miscReg, rt); + } + } + } + ''' +}}; + +def format McrMrc14() {{ + decode_block = ''' + return decodeMcrMrc14(machInst); + ''' +}}; + let {{ header_output = ''' StaticInstPtr diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa index 0ef113607..4a18a55bb 100644 --- a/src/arch/arm/isa/formats/uncond.isa +++ b/src/arch/arm/isa/formats/uncond.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -269,6 +269,8 @@ def format ArmUnconditional() {{ if (bits(op1, 4) == 0) { if (CPNUM == 0xa || CPNUM == 0xb) { return decodeShortFpTransfer(machInst); + } else if (CPNUM == 0xe) { + return decodeMcrMrc14(machInst); } else if (CPNUM == 0xf) { return decodeMcrMrc15(machInst); } diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index d8ee5e88d..831920e1b 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -626,6 +626,58 @@ let {{ decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) exec_output += PredOpExecute.subst(bfiIop) + mrc14code = ''' + CPSR cpsr = Cpsr; + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } + Dest = MiscOp1; + ''' + + mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegOp", + { "code": mrc14code, + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mrc14Iop) + decoder_output += RegRegOpConstructor.subst(mrc14Iop) + exec_output += PredOpExecute.subst(mrc14Iop) + + + mcr14code = ''' + CPSR cpsr = Cpsr; + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } + MiscDest = Op1; + ''' + mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegOp", + { "code": mcr14code, + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) + header_output += RegRegOpDeclare.subst(mcr14Iop) + decoder_output += RegRegOpConstructor.subst(mcr14Iop) + exec_output += PredOpExecute.subst(mcr14Iop) + + mrc14UserIop = InstObjParams("mrc", "Mrc14User", "RegRegOp", + { "code": "Dest = MiscOp1;", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mrc14UserIop) + decoder_output += RegRegOpConstructor.subst(mrc14UserIop) + exec_output += PredOpExecute.subst(mrc14UserIop) + + mcr14UserIop = InstObjParams("mcr", "Mcr14User", "RegRegOp", + { "code": "MiscDest = Op1", + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) + header_output += RegRegOpDeclare.subst(mcr14UserIop) + decoder_output += RegRegOpConstructor.subst(mcr14UserIop) + exec_output += PredOpExecute.subst(mcr14UserIop) + mrc15code = ''' CPSR cpsr = Cpsr; if (cpsr.mode == MODE_USER) { diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index c31818377..286ecc1de 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -45,6 +45,36 @@ namespace ArmISA { +MiscRegIndex +decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) +{ + switch(crn) { + case 0: + switch (opc2) { + case 0: + switch (crm) { + case 0: + return MISCREG_DBGDIDR; + case 1: + return MISCREG_DBGDSCR_INT; + default: + warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", + crn, opc1, crm, opc2); + return NUM_MISCREGS; + } + default: + warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", + crn, opc1, crm, opc2); + return NUM_MISCREGS; + } + default: + warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", + crn, opc1, crm, opc2); + return NUM_MISCREGS; + } + +} + MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) { diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 1f84fa4ca..a20fd0c61 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -86,6 +86,41 @@ namespace ArmISA MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, + // CP14 registers + MISCREG_CP14_START, + MISCREG_DBGDIDR = MISCREG_CP14_START, + MISCREG_DBGDSCR_INT, + MISCREG_DBGDTRRX_INT, + MISCREG_DBGTRTX_INT, + MISCREG_DBGWFAR, + MISCREG_DBGVCR, + MISCREG_DBGECR, + MISCREG_DBGDSCCR, + MISCREG_DBGSMCR, + MISCREG_DBGDTRRX_EXT, + MISCREG_DBGDSCR_EXT, + MISCREG_DBGDTRTX_EXT, + MISCREG_DBGDRCR, + MISCREG_DBGBVR, + MISCREG_DBGBCR, + MISCREG_DBGBVR_M, + MISCREG_DBGBCR_M, + MISCREG_DBGDRAR, + MISCREG_DBGBXVR_M, + MISCREG_DBGOSLAR, + MISCREG_DBGOSSRR, + MISCREG_DBGOSDLR, + MISCREG_DBGPRCR, + MISCREG_DBGPRSR, + MISCREG_DBGDSAR, + MISCREG_DBGITCTRL, + MISCREG_DBGCLAIMSET, + MISCREG_DBGCLAIMCLR, + MISCREG_DBGAUTHSTATUS, + MISCREG_DBGDEVID2, + MISCREG_DBGDEVID1, + MISCREG_DBGDEVID, + // CP15 registers MISCREG_CP15_START, MISCREG_SCTLR = MISCREG_CP15_START, @@ -208,15 +243,51 @@ namespace ArmISA NUM_MISCREGS }; + MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, + unsigned crm, unsigned opc2); + MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2); + const char * const miscRegName[NUM_MISCREGS] = { "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_mon", "spsr_und", "spsr_abt", "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", "mvfr0", "mvfr1", "sctlr_rst", "sev_mailbox", + "DBGDIDR", + "DBGDSCR_INT", + "DBGDTRRX_INT", + "DBGTRTX_INT", + "DBGWFAR", + "DBGVCR", + "DBGECR", + "DBGDSCCR", + "DBGSMCR", + "DBGDTRRX_EXT", + "DBGDSCR_EXT", + "DBGDTRTX_EXT", + "DBGDRCR", + "DBGBVR", + "DBGBCR", + "DBGBVR_M", + "DBGBCR_M", + "DBGDRAR", + "DBGBXVR_M", + "DBGOSLAR", + "DBGOSSRR", + "DBGOSDLR", + "DBGPRCR", + "DBGPRSR", + "DBGDSAR", + "DBGITCTRL", + "DBGCLAIMSET", + "DBGCLAIMCLR", + "DBGAUTHSTATUS", + "DBGDEVID2", + "DBGDEVID1", + "DBGDEVID", "sctlr", "dccisw", "dccimvac", "dccmvac", "contextidr", "tpidrurw", "tpidruro", "tpidrprw", "cp15isb", "cp15dsb", "cp15dmb", "cpacr", -- cgit v1.2.3