From 17f0943398fb403c189dc3f6f4d0d834d56f061c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:19 -0700 Subject: ARM: Add an AddrMode3 format for memory instructions that use address mode 3. --- src/arch/arm/insts/mem.hh | 1 - src/arch/arm/isa/decoder.isa | 238 ++------------------------------------- src/arch/arm/isa/formats/mem.isa | 56 +++++++++ 3 files changed, 65 insertions(+), 230 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh index 80f966e9c..de6e2b954 100644 --- a/src/arch/arm/insts/mem.hh +++ b/src/arch/arm/insts/mem.hh @@ -73,7 +73,6 @@ class Memory : public PredOp { disp = -disp; disp8 = -disp8; - hilo = -hilo; } } diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index cdb228efa..7cc0b198f 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -112,235 +112,15 @@ format DataOp { 0x19: WarnUnimpl::ldrex(); } } - 0xb: decode PUBWL { - format ArmStoreMemory { - 0x0: strh_({{ Mem.uh = Rd; - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x4: strh_i({{ Mem.uh = Rd; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x8: strh_u({{ Mem.uh = Rd; - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xc: strh_ui({{ Mem.uh = Rd; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x10: strh_p({{ Mem.uh = Rd; }}, - {{ EA = Rn - Rm; }}); - 0x12: strh_pw({{ Mem.uh = Rd; - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x14: strh_pi({{ Mem.uh = Rd.uh; }}, - {{ EA = Rn + hilo; }}); - 0x16: strh_piw({{ Mem.uh = Rd; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x18: strh_pu({{ Mem.uh = Rd; }}, - {{ EA = Rn + Rm; }}); - 0x1a: strh_puw({{ Mem.uh = Rd; - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1c: strh_pui({{ Mem.uh = Rd; }}, - {{ EA = Rn + hilo; }}); - 0x1e: strh_puiw({{ Mem.uh = Rd; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - } - format ArmLoadMemory { - 0x1: ldrh_l({{ Rd = Mem.uh; - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x5: ldrh_il({{ Rd = Mem.uh; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x9: ldrh_ul({{ Rd = Mem.uh; - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xd: ldrh_uil({{ Rd = Mem.uh; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x11: ldrh_pl({{ Rd = Mem.uh; }}, - {{ EA = Rn - Rm; }}); - 0x13: ldrh_pwl({{ Rd = Mem.uh; - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x15: ldrh_pil({{ Rd = Mem.uh; }}, - {{ EA = Rn + hilo; }}); - 0x17: ldrh_piwl({{ Rd = Mem.uh; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x19: ldrh_pul({{ Rd = Mem.uh; }}, - {{ EA = Rn + Rm; }}); - 0x1b: ldrh_puwl({{ Rd = Mem.uh; - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1d: ldrh_puil({{ Rd = Mem.uh; }}, - {{ EA = Rn + hilo; }}); - 0x1f: ldrh_puiwl({{ Rd = Mem.uh; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - } - } - format ArmLoadMemory { - 0xd: decode PUBWL { - 0x0: ldrd_({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x1: ldrsb_l({{ Rd = Mem.sb; - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x4: ldrd_i({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x5: ldrsb_il({{ Rd = Mem.sb; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x8: ldrd_u({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0x9: ldrsb_ul({{ Rd = Mem.sb; - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xc: ldrd_ui({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0xd: ldrsb_uil({{ Rd = Mem.sb; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x10: ldrd_p({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); }}, - {{ EA = Rn - Rm; }}); - 0x11: ldrsb_pl({{ Rd = Mem.sb; }}, - {{ EA = Rn - Rm; }}); - 0x12: ldrd_pw({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x13: ldrsb_pwl({{ Rd = Mem.sb; - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x14: ldrd_pi({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); }}, - {{ EA = Rn + hilo; }}); - 0x15: ldrsb_pil({{ Rd = Mem.sb; }}, - {{ EA = Rn + hilo; }}); - 0x16: ldrd_piw({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x17: ldrsb_piwl({{ Rd = Mem.sb; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x18: ldrd_pu({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); }}, - {{ EA = Rn + Rm; }}); - 0x19: ldrsb_pul({{ Rd = Mem.sb; }}, - {{ EA = Rn + Rm; }}); - 0x1a: ldrd_puw({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1b: ldrsb_puwl({{ Rd = Mem.sb; - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1c: ldrd_pui({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); }}, - {{ EA = Rn + hilo; }}); - 0x1d: ldrsb_puil({{ Rd = Mem.sb; }}, - {{ EA = Rn + hilo; }}); - 0x1e: ldrd_puiw({{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x1f: ldrsb_puiwl({{ Rd = Mem.sb; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - } - 0xf: decode PUBWL { - 0x1: ldrsh_l({{ Rd = Mem.sh; - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x5: ldrsh_il({{ Rd = Mem.sh; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x9: ldrsh_ul({{ Rd = Mem.sh; - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xd: ldrsh_uil({{ Rd = Mem.sh; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x11: ldrsh_pl({{ Rd = Mem.sh; }}, - {{ EA = Rn - Rm; }}); - 0x13: ldrsh_pwl({{ Rd = Mem.sh; - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x15: ldrsh_pil({{ Rd = Mem.sh; }}, - {{ EA = Rn + hilo; }}); - 0x17: ldrsh_piwl({{ Rd = Mem.sh; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x19: ldrsh_pul({{ Rd = Mem.sh; }}, - {{ EA = Rn + Rm; }}); - 0x1b: ldrsh_puwl({{ Rd = Mem.sh; - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1d: ldrsh_puil({{ Rd = Mem.sh; }}, - {{ EA = Rn + hilo; }}); - 0x1f: ldrsh_puiwl({{ Rd = Mem.sh; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - format ArmStoreMemory { - 0x0: strd_({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x4: strd_i({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x8: strd_u({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xc: strd_ui({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x10: strd_p({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); }}, - {{ EA = Rn - Rm; }}); - 0x12: strd_pw({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x14: strd_pi({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); }}, - {{ EA = Rn + hilo; }}); - 0x16: strd_piw({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x18: strd_pu({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); }}, - {{ EA = Rn + Rm; }}); - 0x1a: strd_puw({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1c: strd_pui({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); }}, - {{ EA = Rn + hilo; }}); - 0x1e: strd_puiw({{ Mem.ud = (uint64_t)Rde | - ((uint64_t)Rdo << 32); - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - } - } + format AddrMode3 { + 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, + load, {{ Rd = Mem.uh; }}); + 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); + Rdo = bits(Mem.ud, 63, 32); }}, + load, {{ Rd = Mem.sb; }}); + 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | + (Rdo.ud << 32); }}, + load, {{ Rd = Mem.sh; }}); } } 0: decode IS_MISC { diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index c8ac19c61..a154cac60 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -454,6 +454,62 @@ def template MiscCompleteAcc {{ } }}; +let {{ + def buildPUBWLCase(p, u, b, w, l): + return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0) + + def buildMode3Inst(p, u, i, w, type, code, mnem): + op = ("-", "+")[u] + offset = ("%s Rm", "%s hilo")[i] % op + ea_code = "EA = Rn %s;" % ("", offset)[p] + if p == 0 or w == 1: + code += "Rn = Rn %s;" % offset + suffix = "_P%dU%dI%dW%d" % (p, u, i, w) + return LoadStoreBase(mnem, mnem.capitalize() + suffix, + ea_code, code, mem_flags = [], inst_flags = [], + exec_template_base = type.capitalize()) +}}; + +def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{ + l0Code = ArmGenericCodeSubs(l0Code); + l1Code = ArmGenericCodeSubs(l1Code); + + header_output = decoder_output = exec_output = "" + decode_block = "switch(PUBWL) {\n" + (l0Mnem, l1Mnem) = name.split("_"); + + # Loop over all the values of p, u, i, w and l and build instructions and + # a decode block for them. + for (l, type, code, mnem) in ((0, l0Type, l0Code, l0Mnem), + (1, l1Type, l1Code, l1Mnem)): + for p in (0, 1): + wset = (0, 1) + if (p == 0): + wset = (0,) + for u in (0, 1): + for i in (0, 1): + for w in wset: + (new_header_output, + new_decoder_output, + new_decode_block, + new_exec_output) = buildMode3Inst(p, u, i, w, + type, code, mnem) + header_output += new_header_output + decoder_output += new_decoder_output + exec_output += new_exec_output + decode_block += ''' + case %#x: + {%s} + break; + ''' % (buildPUBWLCase(p,u,i,w,l), new_decode_block) + + decode_block += ''' + default: + return new Unknown(machInst); + break; + }''' +}}; + def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, mem_flags = [], inst_flags = []) {{ ea_code = ArmGenericCodeSubs(ea_code) -- cgit v1.2.3