From 18a30524d6afb397df1af764e8dc80ff4e7cdb98 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 8 Apr 2009 22:22:49 -0700 Subject: alpha: get rid of all turbolaser remnants --- src/arch/alpha/SConsopts | 4 ---- src/arch/alpha/ev5.hh | 13 ------------- src/arch/alpha/tlb.cc | 32 +++----------------------------- 3 files changed, 3 insertions(+), 46 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/SConsopts b/src/arch/alpha/SConsopts index b418e27c8..4af7a4daf 100644 --- a/src/arch/alpha/SConsopts +++ b/src/arch/alpha/SConsopts @@ -31,7 +31,3 @@ Import('*') all_isa_list.append('alpha') - -# Alpha can be compiled with Turbolaser support instead of Tsunami -sticky_vars.Add(BoolVariable('ALPHA_TLASER', - 'Model Alpha TurboLaser platform (vs. Tsunami)', False)) diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh index 1915d822b..a135ac506 100644 --- a/src/arch/alpha/ev5.hh +++ b/src/arch/alpha/ev5.hh @@ -33,17 +33,11 @@ #ifndef __ARCH_ALPHA_EV5_HH__ #define __ARCH_ALPHA_EV5_HH__ -#include "config/alpha_tlaser.hh" #include "arch/alpha/isa_traits.hh" namespace AlphaISA { -#if ALPHA_TLASER -const uint64_t AsnMask = ULL(0x7f); -#else const uint64_t AsnMask = ULL(0xff); -#endif - const int VAddrImplBits = 43; const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; const Addr VAddrUnImplMask = ~VAddrImplMask; @@ -53,13 +47,8 @@ inline Addr VAddrOffset(Addr a) { return a & PageOffset; } inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } -#if ALPHA_TLASER -inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } -const int PAddrImplBits = 40; -#else inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } const int PAddrImplBits = 44; // for Tsunami -#endif const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; const Addr PAddrUncachedBit39 = ULL(0x8000000000); const Addr PAddrUncachedBit40 = ULL(0x10000000000); @@ -69,12 +58,10 @@ const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> inline Addr Phys2K0Seg(Addr addr) { -#if !ALPHA_TLASER if (addr & PAddrUncachedBit43) { addr &= PAddrUncachedMask; addr |= PAddrUncachedBit40; } -#endif return addr | K0SegBase; } diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index d4f31b421..d9e9dd342 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -39,7 +39,6 @@ #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" -#include "config/alpha_tlaser.hh" #include "cpu/thread_context.hh" using namespace std; @@ -215,12 +214,7 @@ TLB::checkCacheability(RequestPtr &req, bool itb) */ -#if ALPHA_TLASER - if (req->getPaddr() & PAddrUncachedBit39) -#else - if (req->getPaddr() & PAddrUncachedBit43) -#endif - { + if (req->getPaddr() & PAddrUncachedBit43) { // IPR memory space not implemented if (PAddrIprSpace(req->getPaddr())) { return new UnimpFault("IPR memory space not implemented!"); @@ -228,11 +222,9 @@ TLB::checkCacheability(RequestPtr &req, bool itb) // mark request as uncacheable req->setFlags(Request::UNCACHEABLE); -#if !ALPHA_TLASER // Clear bits 42:35 of the physical address (10-2 in // Tsunami manual) req->setPaddr(req->getPaddr() & PAddrUncachedMask); -#endif } // We shouldn't be able to read from an uncachable address in Alpha as // we don't have a ROM and we don't want to try to fetch from a device @@ -398,13 +390,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 -#if ALPHA_TLASER - if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->getVaddr()) == 2) -#else - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) -#endif - { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { // only valid in kernel mode if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != mode_kernel) { @@ -414,14 +400,11 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) req->setPaddr(req->getVaddr() & PAddrImplMask); -#if !ALPHA_TLASER // sign extend the physical address properly if (req->getPaddr() & PAddrUncachedBit40) req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); else req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); -#endif - } else { // not a physical address: need to look up pte int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); @@ -495,13 +478,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) } // Check for "superpage" mapping -#if ALPHA_TLASER - if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->getVaddr()) == 2) -#else - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) -#endif - { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { // only valid in kernel mode if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != mode_kernel) { @@ -515,14 +492,11 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) req->setPaddr(req->getVaddr() & PAddrImplMask); -#if !ALPHA_TLASER // sign extend the physical address properly if (req->getPaddr() & PAddrUncachedBit40) req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); else req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); -#endif - } else { if (write) write_accesses++; -- cgit v1.2.3