From 19e05d7e8d4a5e9a6f3bb60d3530e2de6a61fee0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:14 -0500 Subject: ARM: Move the VFP data operation decode into a function. --- src/arch/arm/isa/decoder/arm.isa | 4 +- src/arch/arm/isa/decoder/thumb.isa | 8 +-- src/arch/arm/isa/decoder/vfp.isa | 83 -------------------------- src/arch/arm/isa/formats/fp.isa | 118 +++++++++++++++++++++++++++++++++++++ 4 files changed, 121 insertions(+), 92 deletions(-) delete mode 100644 src/arch/arm/isa/decoder/vfp.isa (limited to 'src/arch') diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index f453d8299..163da5ca0 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -143,9 +143,7 @@ format DataOp { 0x7: decode OPCODE_24 { 0: decode OPCODE_4 { 0: decode CPNUM { - 0xa, 0xb: decode OPCODE_23_20 { -##include "vfp.isa" - } + 0xa, 0xb: VfpData::vfpData(); } // CPNUM 1: decode CPNUM { // 27-24=1110,4 ==1 1: decode OPCODE_15_12 { diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index d618f6b35..6c1dd7d57 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -80,9 +80,7 @@ default: decode HTOPCODE_9_8 { 0x2: decode LTOPCODE_4 { 0x0: decode LTCOPROC { - 0xa, 0xb: decode OPCODE_23_20 { -##include "vfp.isa" - } + 0xa, 0xb: VfpData::vfpData(); default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { @@ -138,9 +136,7 @@ default: decode HTOPCODE_9_8 { 0x2: decode LTOPCODE_4 { 0x0: decode LTCOPROC { - 0xa, 0xb: decode OPCODE_23_20 { -##include "vfp.isa" - } + 0xa, 0xb: VfpData::vfpData(); default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { diff --git a/src/arch/arm/isa/decoder/vfp.isa b/src/arch/arm/isa/decoder/vfp.isa deleted file mode 100644 index 65da0abc3..000000000 --- a/src/arch/arm/isa/decoder/vfp.isa +++ /dev/null @@ -1,83 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2010 ARM Limited -// All rights reserved -// -// The license below extends only to copyright in the software and shall -// not be construed as granting a license to any other intellectual -// property including but not limited to intellectual property relating -// to a hardware implementation of the functionality of the software -// licensed hereunder. You may use the software subject to the license -// terms below provided that you ensure that this notice is replicated -// unmodified and in its entirety in all distributions of the software, -// modified or unmodified, in source code or in binary form. -// -// Copyright (c) 2009 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Gabe Black - - -// There needs to be a decode statement in the file that includes this since -// the isa_parser can't handle a case and what it corresponds with spanning -// lines. it should decode bits 23 through 20. - -format FloatOp { - 0x0, 0x4: WarnUnimpl::vmla(); // vmls - 0x1, 0x5: WarnUnimpl::vnmla(); // vnmls, vnmul - 0x2, 0x6: decode OPCODE_6 { - 0x0: WarnUnimpl::vmul(); - 0x1: WarnUnimpl::vnmla(); // vnmls, vnmul - } - 0x3, 0x7: decode OPCODE_6 { - 0x0: WarnUnimpl::vadd(); - 0x1: WarnUnimpl::vsub(); - } - 0x8, 0xc: WarnUnimpl::vdiv(); - 0xb, 0xf: decode OPCODE_6 { - 0x0: WarnUnimpl::vmov(); // immediate - 0x1: decode OPCODE_19_16 { - 0x0: decode OPCODE_7 { - 0x0: WarnUnimpl::vmov(); // register - 0x1: WarnUnimpl::vabs(); - } - 0x1: decode OPCODE_7 { - 0x0: WarnUnimpl::vneg(); - 0x1: WarnUnimpl::vsqrt(); - } - 0x2, 0x3: WarnUnimpl::vcvtb(); // vcvtt - 0x4, 0x5: WarnUnimpl::vcmp(); // vcmpe double to single - 0x7: decode OPCODE_7 { - 0x0: WarnUnimpl::vcvt(); // double and single - } - 0x8: WarnUnimpl::vcvt(); // vcvtr fp and int - 0xa, 0xb: WarnUnimpl::vcvt(); // fp and fixed point - 0xc, 0xd: WarnUnimpl::vcvt(); // vcvtr fp and int - 0xe, 0xf: WarnUnimpl::vcvt(); // fp and fixed point - } - } -} - diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 560a16edf..848ce907c 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -467,3 +467,121 @@ def format ShortFpTransfer() {{ return decodeShortFpTransfer(machInst); ''' }}; + +let {{ + header_output = ''' + StaticInstPtr + decodeVfpData(ExtMachInst machInst); + ''' + decoder_output = ''' + StaticInstPtr + decodeVfpData(ExtMachInst machInst) + { + const uint32_t opc1 = bits(machInst, 23, 20); + const uint32_t opc2 = bits(machInst, 19, 16); + const uint32_t opc3 = bits(machInst, 7, 6); + //const uint32_t opc4 = bits(machInst, 3, 0); + switch (opc1 & 0xb /* 1011 */) { + case 0x0: + return new WarnUnimplemented("vmla, vmls", machInst); + case 0x2: + if ((opc3 & 0x1) == 0) { + return new WarnUnimplemented("vmul", machInst); + } + case 0x1: + return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst); + case 0x3: + if ((opc3 & 0x1) == 0) { + return new WarnUnimplemented("vadd", machInst); + } else { + return new WarnUnimplemented("vsub", machInst); + } + case 0x8: + if ((opc3 & 0x1) == 0) { + return new WarnUnimplemented("vdiv", machInst); + } + break; + case 0xb: + if ((opc3 & 0x1) == 0) { + uint32_t vd; + const uint32_t baseImm = + bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); + if (bits(machInst, 8) == 0) { + vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); + uint32_t imm = vfp_modified_imm(baseImm, false); + return new VmovImmS(machInst, (IntRegIndex)vd, imm); + } else { + vd = (bits(machInst, 22) << 5) | + (bits(machInst, 15, 12) << 1); + uint64_t imm = vfp_modified_imm(baseImm, true); + return new VmovImmD(machInst, (IntRegIndex)vd, imm); + } + } + switch (opc2) { + case 0x0: + if (opc3 == 1) { + uint32_t vd; + uint32_t vm; + if (bits(machInst, 8) == 0) { + vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); + vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); + return new VmovRegS(machInst, + (IntRegIndex)vd, (IntRegIndex)vm); + } else { + vd = (bits(machInst, 22) << 5) | + (bits(machInst, 15, 12) << 1); + vm = (bits(machInst, 5) << 5) | + (bits(machInst, 3, 0) << 1); + return new VmovRegD(machInst, + (IntRegIndex)vd, (IntRegIndex)vm); + } + } else { + return new WarnUnimplemented("vabs", machInst); + } + case 0x1: + if (opc3 == 1) { + return new WarnUnimplemented("vneg", machInst); + } else { + return new WarnUnimplemented("vsqrt", machInst); + } + case 0x2: + case 0x3: + // Between half and single precision. + return new WarnUnimplemented("vcvtb, vcvtt", machInst); + case 0x4: + case 0x5: + return new WarnUnimplemented("vcmp, vcmpe", machInst); + case 0x7: + if (opc3 == 0x3) { + // Between double and single precision. + return new WarnUnimplemented("vcvt", machInst); + } + break; + case 0x8: + // Between FP and int. + return new WarnUnimplemented("vcvt, vcvtr", machInst); + case 0xa: + case 0xb: + // Between FP and fixed point. + return new WarnUnimplemented("vcvt", machInst); + case 0xc: + case 0xd: + // Between FP and int. + return new WarnUnimplemented("vcvt, vcvtr", machInst); + case 0xe: + case 0xf: + // Between FP and fixed point. + return new WarnUnimplemented("vcvt", machInst); + } + break; + } + return new Unknown(machInst); + } + ''' +}}; + +def format VfpData() {{ + decode_block = ''' + return decodeVfpData(machInst); + ''' +}}; -- cgit v1.2.3