From 25884a87733cd35ef6613aaef9a8a08194267552 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: Registers: Get rid of the float register width parameter. --- src/arch/alpha/floatregfile.hh | 33 -------- src/arch/alpha/regfile.hh | 24 ------ src/arch/arm/regfile/float_regfile.hh | 57 ++------------ src/arch/arm/regfile/regfile.hh | 32 ++------ src/arch/arm/types.hh | 8 +- src/arch/isa_parser.py | 49 +++--------- src/arch/mips/isa/formats/fp.isa | 34 +++----- src/arch/mips/regfile.cc | 28 +------ src/arch/mips/regfile/float_regfile.cc | 95 +++------------------- src/arch/mips/regfile/float_regfile.hh | 26 ++---- src/arch/mips/regfile/regfile.cc | 36 ++------- src/arch/mips/regfile/regfile.hh | 8 +- src/arch/mips/types.hh | 8 +- src/arch/sparc/floatregfile.cc | 139 +++------------------------------ src/arch/sparc/floatregfile.hh | 28 ++----- src/arch/sparc/regfile.cc | 33 +------- src/arch/sparc/regfile.hh | 8 -- src/arch/sparc/types.hh | 4 +- src/arch/x86/floatregfile.cc | 8 +- src/arch/x86/floatregfile.hh | 14 +--- src/arch/x86/regfile.cc | 33 +------- src/arch/x86/regfile.hh | 8 -- 22 files changed, 106 insertions(+), 607 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh index f6abb1f86..eb8a92d89 100644 --- a/src/arch/alpha/floatregfile.hh +++ b/src/arch/alpha/floatregfile.hh @@ -42,18 +42,9 @@ class Checkpoint; namespace AlphaISA { -const int SingleWidth = 32; -const int SingleBytes = SingleWidth / 4; -const int DoubleWidth = 64; -const int DoubleBytes = DoubleWidth / 4; -const int QuadWidth = 128; -const int QuadBytes = QuadWidth / 4; - class FloatRegFile { public: - static const int regWidth = DoubleWidth; - union { uint64_t q[NumFloatRegs]; // integer qword view double d[NumFloatRegs]; // double-precision floating point view @@ -70,48 +61,24 @@ class FloatRegFile return d[floatReg]; } - FloatReg - readReg(int floatReg, int width) - { - return readReg(floatReg); - } - FloatRegBits readRegBits(int floatReg) { return q[floatReg]; } - FloatRegBits - readRegBits(int floatReg, int width) - { - return readRegBits(floatReg); - } - void setReg(int floatReg, const FloatReg &val) { d[floatReg] = val; } - void - setReg(int floatReg, const FloatReg &val, int width) - { - setReg(floatReg, val); - } - void setRegBits(int floatReg, const FloatRegBits &val) { q[floatReg] = val; } - void - setRegBits(int floatReg, const FloatRegBits &val, int width) - { - setRegBits(floatReg, val); - } - }; } // namespace AlphaISA diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 59b76efd5..0a39a94a9 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -112,48 +112,24 @@ class RegFile { return floatRegFile.d[floatReg]; } - FloatReg - readFloatReg(int floatReg, int width) - { - return readFloatReg(floatReg); - } - FloatRegBits readFloatRegBits(int floatReg) { return floatRegFile.q[floatReg]; } - FloatRegBits - readFloatRegBits(int floatReg, int width) - { - return readFloatRegBits(floatReg); - } - void setFloatReg(int floatReg, const FloatReg &val) { floatRegFile.d[floatReg] = val; } - void - setFloatReg(int floatReg, const FloatReg &val, int width) - { - setFloatReg(floatReg, val); - } - void setFloatRegBits(int floatReg, const FloatRegBits &val) { floatRegFile.q[floatReg] = val; } - void - setFloatRegBits(int floatReg, const FloatRegBits &val, int width) - { - setFloatRegBits(floatReg, val); - } - IntReg readIntReg(int intReg) { diff --git a/src/arch/arm/regfile/float_regfile.hh b/src/arch/arm/regfile/float_regfile.hh index 757f5f0df..fc4515b17 100644 --- a/src/arch/arm/regfile/float_regfile.hh +++ b/src/arch/arm/regfile/float_regfile.hh @@ -75,21 +75,12 @@ namespace ArmISA Cause_Field = 11 }; - const int SingleWidth = 32; - const int SingleBytes = SingleWidth / 4; - - const int DoubleWidth = 64; - const int DoubleBytes = DoubleWidth / 4; - - const int QuadWidth = 128; - const int QuadBytes = QuadWidth / 4; - class FloatRegFile { protected: union { FloatRegBits qregs[NumFloatRegs]; - FloatRegVal regs[NumFloatRegs]; + FloatReg regs[NumFloatRegs]; }; public: @@ -107,38 +98,17 @@ namespace ArmISA regs[15] = 10.0; } - FloatRegVal readReg(int floatReg, int width) + FloatReg readReg(int floatReg) { return regs[floatReg]; } - FloatRegBits readRegBits(int floatReg, int width) + FloatRegBits readRegBits(int floatReg) { - //return qregs[floatReg]; - switch(width) - { - case SingleWidth: - { - union { - float f; - uint32_t i; - } s; - s.f = (float) regs[floatReg]; - return s.i; - } - case DoubleWidth: - { - uint64_t tmp = (qregs[floatReg]<<32|qregs[floatReg]>>32); - return tmp; - } - default: - panic("Attempted to read a %d bit floating point " - "register!", width); - - } + return qregs[floatReg]; } - Fault setReg(int floatReg, const FloatRegVal &val, int width) + Fault setReg(int floatReg, const FloatReg &val) { if (floatReg > 7) panic("Writing to a hard-wired FP register"); @@ -146,23 +116,12 @@ namespace ArmISA return NoFault; } - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) + Fault setRegBits(int floatReg, const FloatRegBits &val) { if (floatReg > 7) panic("Writing to a hard-wired FP register"); - switch(width) - { - case DoubleWidth: - { - uint64_t tmp = (val << 32 | val >> 32); - qregs[floatReg] = tmp; - return NoFault; - } - case SingleWidth: - default: - panic("Attempted to write a %d bit floating point " - "register!", width); - } + qregs[floatReg] = val; + return NoFault; } void serialize(std::ostream &os) diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh index c432c0c28..6eefe5914 100644 --- a/src/arch/arm/regfile/regfile.hh +++ b/src/arch/arm/regfile/regfile.hh @@ -57,44 +57,24 @@ namespace ArmISA floatRegFile.clear(); } - FloatRegVal readFloatReg(int floatReg) + FloatReg readFloatReg(int floatReg) { - return floatRegFile.readReg(floatReg,SingleWidth); - } - - FloatRegVal readFloatReg(int floatReg, int width) - { - return floatRegFile.readReg(floatReg,width); + return floatRegFile.readReg(floatReg); } FloatRegBits readFloatRegBits(int floatReg) { - return floatRegFile.readRegBits(floatReg,SingleWidth); - } - - FloatRegBits readFloatRegBits(int floatReg, int width) - { - return floatRegFile.readRegBits(floatReg,width); + return floatRegFile.readRegBits(floatReg); } - void setFloatReg(int floatReg, const FloatRegVal &val) + void setFloatReg(int floatReg, const FloatReg &val) { - floatRegFile.setReg(floatReg, val, SingleWidth); - } - - void setFloatReg(int floatReg, const FloatRegVal &val, int width) - { - floatRegFile.setReg(floatReg, val, width); + floatRegFile.setReg(floatReg, val); } void setFloatRegBits(int floatReg, const FloatRegBits &val) { - floatRegFile.setRegBits(floatReg, val, SingleWidth); - } - - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width) - { - floatRegFile.setRegBits(floatReg, val, width); + floatRegFile.setRegBits(floatReg, val); } IntReg readIntReg(int intReg) diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 3a0fdf2a5..82d1c332c 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -120,12 +120,8 @@ namespace ArmISA // Need to use 64 bits to make sure that read requests get handled properly // floating point register file entry type - typedef uint32_t FloatReg32; - typedef uint64_t FloatReg64; - typedef uint64_t FloatRegBits; - - typedef double FloatRegVal; - typedef double FloatReg; + typedef uint32_t FloatRegBits; + typedef float FloatReg; // cop-0/cop-1 system control register typedef uint64_t MiscReg; diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 8facd5cce..4c4a26bcf 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1173,10 +1173,9 @@ def buildOperandTypeMap(userDict, lineno): # (e.g., "32-bit integer register"). # class Operand(object): - def buildReadCode(self, func = None, width = None): + def buildReadCode(self, func = None): code = self.read_code % {"name": self.base_name, "func": func, - "width": width, "op_idx": self.src_reg_idx, "reg_idx": self.reg_spec, "size": self.size, @@ -1188,14 +1187,13 @@ class Operand(object): return '%s = %s;\n' % \ (self.base_name, code) - def buildWriteCode(self, func = None, width = None): + def buildWriteCode(self, func = None): if (self.size != self.dflt_size and self.is_signed): final_val = 'sext<%d>(%s)' % (self.size, self.base_name) else: final_val = self.base_name code = self.write_code % {"name": self.base_name, "func": func, - "width": width, "op_idx": self.dest_reg_idx, "reg_idx": self.reg_spec, "size": self.size, @@ -1358,29 +1356,15 @@ class FloatRegOperand(Operand): def makeRead(self): bit_select = 0 - width = 0; - if (self.ctype == 'float'): - func = 'readFloatRegOperand' - width = 32; - elif (self.ctype == 'double'): + if (self.ctype == 'float' or self.ctype == 'double'): func = 'readFloatRegOperand' - width = 64; else: func = 'readFloatRegOperandBits' - if (self.ctype == 'uint32_t'): - width = 32; - elif (self.ctype == 'uint64_t'): - width = 64; if (self.size != self.dflt_size): bit_select = 1 - if width: - base = 'xc->%s(this, %d, %d)' % \ - (func, self.src_reg_idx, width) - else: - base = 'xc->%s(this, %d)' % \ - (func, self.src_reg_idx) + base = 'xc->%s(this, %d)' % (func, self.src_reg_idx) if self.read_code != None: - return self.buildReadCode(func, width) + return self.buildReadCode(func) if bit_select: return '%s = bits(%s, %d, 0);\n' % \ (self.base_name, base, self.size-1) @@ -1390,36 +1374,23 @@ class FloatRegOperand(Operand): def makeWrite(self): final_val = self.base_name final_ctype = self.ctype - widthSpecifier = '' - width = 0 - if (self.ctype == 'float'): - width = 32 - func = 'setFloatRegOperand' - elif (self.ctype == 'double'): - width = 64 + if (self.ctype == 'float' or self.ctype == 'double'): func = 'setFloatRegOperand' - elif (self.ctype == 'uint32_t'): - func = 'setFloatRegOperandBits' - width = 32 - elif (self.ctype == 'uint64_t'): + elif (self.ctype == 'uint32_t' or self.ctype == 'uint64_t'): func = 'setFloatRegOperandBits' - width = 64 else: func = 'setFloatRegOperandBits' final_ctype = 'uint%d_t' % self.dflt_size if (self.size != self.dflt_size and self.is_signed): final_val = 'sext<%d>(%s)' % (self.size, self.base_name) if self.write_code != None: - return self.buildWriteCode(func, width) - if width: - widthSpecifier = ', %d' % width + return self.buildWriteCode(func) wb = ''' { %s final_val = %s; - xc->%s(this, %d, final_val%s);\n + xc->%s(this, %d, final_val);\n if (traceData) { traceData->setData(final_val); } - }''' % (final_ctype, final_val, func, self.dest_reg_idx, - widthSpecifier) + }''' % (final_ctype, final_val, func, self.dest_reg_idx) return wb class ControlRegOperand(Operand): diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 74200a74a..52fcd0724 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -104,25 +104,14 @@ output exec {{ Trace::InstRecord *traceData) { uint64_t mips_nan = 0; - T src_op = 0; - int size = sizeof(src_op) * 8; + assert(sizeof(T) == 4); for (int i = 0; i < inst->numSrcRegs(); i++) { - uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size); - - if (isNan(&src_bits, size) ) { - if (isSnan(&src_bits, size)) { - switch (size) - { - case 32: mips_nan = MIPS32_QNAN; break; - case 64: mips_nan = MIPS64_QNAN; break; - default: panic("Unsupported Floating Point Size (%d)", size); - } - } else { - mips_nan = src_bits; - } + uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0); - xc->setFloatRegOperandBits(inst, 0, mips_nan, size); + if (isNan(&src_bits, 32) ) { + mips_nan = MIPS32_QNAN; + xc->setFloatRegOperandBits(inst, 0, mips_nan); if (traceData) { traceData->setData(mips_nan); } return true; } @@ -137,18 +126,13 @@ output exec {{ { uint64_t mips_nan = 0; T src_op = dest_val; - int size = sizeof(src_op) * 8; + assert(sizeof(T) == 4); - if (isNan(&src_op, size)) { - switch (size) - { - case 32: mips_nan = MIPS32_QNAN; break; - case 64: mips_nan = MIPS64_QNAN; break; - default: panic("Unsupported Floating Point Size (%d)", size); - } + if (isNan(&src_op, 32)) { + mips_nan = MIPS32_QNAN; //Set value to QNAN - cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); + cpu->setFloatRegOperandBits(inst, 0, mips_nan); //Read FCSR from FloatRegFile uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc index 4cc6725f7..e9adb5d05 100644 --- a/src/arch/mips/regfile.cc +++ b/src/arch/mips/regfile.cc @@ -100,42 +100,22 @@ RegFile::setMiscReg(int miscReg, const MiscReg &val, FloatRegVal RegFile::readFloatReg(int floatReg) { - return floatRegFile.readReg(floatReg,SingleWidth); -} - -FloatRegVal RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg,width); + return floatRegFile.readReg(floatReg); } FloatRegBits RegFile::readFloatRegBits(int floatReg) { - return floatRegFile.readRegBits(floatReg,SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg,width); + return floatRegFile.readRegBits(floatReg); } Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val) { - return floatRegFile.setReg(floatReg, val, SingleWidth); -} - -Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width) -{ - return floatRegFile.setReg(floatReg, val, width); + return floatRegFile.setReg(floatReg, val); } Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) { - return floatRegFile.setRegBits(floatReg, val, SingleWidth); -} - -Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - return floatRegFile.setRegBits(floatReg, val, width); + return floatRegFile.setRegBits(floatReg, val); } Addr RegFile::readPC() diff --git a/src/arch/mips/regfile/float_regfile.cc b/src/arch/mips/regfile/float_regfile.cc index 2b32bd3af..884c59cc0 100644 --- a/src/arch/mips/regfile/float_regfile.cc +++ b/src/arch/mips/regfile/float_regfile.cc @@ -38,114 +38,43 @@ using namespace std; void FloatRegFile::clear() { - bzero(®s, sizeof(regs)); + bzero(regs.q, sizeof(regs.q)); } -double -FloatRegFile::readReg(int floatReg, int width, ThreadID tid) +FloatReg +FloatRegFile::readReg(int floatReg) { - switch(width) - { - case SingleWidth: - { - void *float_ptr = ®s[floatReg]; - return *(float *) float_ptr; - } - - case DoubleWidth: - { - uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; - void *double_ptr = &double_val; - return *(double *) double_ptr; - } - - default: - panic("Attempted to read a %d bit floating point register!", width); - } + return regs.s[floatReg]; } FloatRegBits -FloatRegFile::readRegBits(int floatReg, int width, ThreadID tid) +FloatRegFile::readRegBits(int floatReg) { - if (floatReg < NumFloatArchRegs - 1) { - switch(width) - { - case SingleWidth: - return regs[floatReg]; - - case DoubleWidth: - return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; - - default: - panic("Attempted to read a %d bit floating point register!", width); - } - } else { - if (width > SingleWidth) - assert("Control Regs are only 32 bits wide"); - - return regs[floatReg]; - } + return regs.q[floatReg]; } Fault -FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, - ThreadID tid) +FloatRegFile::setReg(int floatReg, const FloatReg &val) { - switch(width) - { - case SingleWidth: - { - float temp = val; - void *float_ptr = &temp; - regs[floatReg] = *(FloatReg32 *) float_ptr; - break; - } - - case DoubleWidth: - { - const void *double_ptr = &val; - FloatReg64 temp_double = *(FloatReg64 *) double_ptr; - regs[floatReg + 1] = bits(temp_double, 63, 32); - regs[floatReg] = bits(temp_double, 31, 0); - break; - } - - default: - panic("Attempted to read a %d bit floating point register!", width); - } - + regs.s[floatReg] = val; return NoFault; } Fault -FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width, - ThreadID tid) +FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val) { - switch(width) - { - case SingleWidth: - regs[floatReg] = val; - break; - - case DoubleWidth: - regs[floatReg + 1] = bits(val, 63, 32); - regs[floatReg] = bits(val, 31, 0); - break; - - default: - panic("Attempted to read a %d bit floating point register!", width); - } + regs.q[floatReg] = val; return NoFault; } void FloatRegFile::serialize(std::ostream &os) { - SERIALIZE_ARRAY(regs, NumFloatRegs); + SERIALIZE_ARRAY(regs.q, NumFloatRegs); } void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) { - UNSERIALIZE_ARRAY(regs, NumFloatRegs); + UNSERIALIZE_ARRAY(regs.q, NumFloatRegs); } diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index afe6701c5..5a641887c 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -70,30 +70,20 @@ namespace MipsISA Cause_Field = 11 }; - const int SingleWidth = 32; - const int SingleBytes = SingleWidth / 4; - - const int DoubleWidth = 64; - const int DoubleBytes = DoubleWidth / 4; - - const int QuadWidth = 128; - const int QuadBytes = QuadWidth / 4; - class FloatRegFile { protected: - FloatReg32 regs[NumFloatRegs]; + union { + FloatReg s[NumFloatRegs]; + FloatRegBits q[NumFloatRegs]; + } regs; public: - static const int regWidth = SingleWidth; - void clear(); - double readReg(int floatReg, int width, ThreadID tid = 0); - FloatRegBits readRegBits(int floatReg, int width, ThreadID tid = 0); - Fault setReg(int floatReg, const FloatRegVal &val, int width, - ThreadID tid = 0); - Fault setRegBits(int floatReg, const FloatRegBits &val, int width, - ThreadID tid = 0); + FloatReg readReg(int floatReg); + FloatRegBits readRegBits(int floatReg); + Fault setReg(int floatReg, const FloatReg &val); + Fault setRegBits(int floatReg, const FloatRegBits &val); void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc index 2b70ea9bd..e7ba5a2ca 100644 --- a/src/arch/mips/regfile/regfile.cc +++ b/src/arch/mips/regfile/regfile.cc @@ -64,52 +64,28 @@ RegFile::setIntReg(int intReg, const IntReg &val) return intRegFile.setReg(intReg, val); } -FloatRegVal +FloatReg RegFile::readFloatReg(int floatReg) { - return floatRegFile.readReg(floatReg,SingleWidth); -} - -FloatRegVal -RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg,width); + return floatRegFile.readReg(floatReg); } FloatRegBits RegFile::readFloatRegBits(int floatReg) { - return floatRegFile.readRegBits(floatReg,SingleWidth); -} - -FloatRegBits -RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg,width); + return floatRegFile.readRegBits(floatReg); } Fault -RegFile::setFloatReg(int floatReg, const FloatRegVal &val) +RegFile::setFloatReg(int floatReg, const FloatReg &val) { - return floatRegFile.setReg(floatReg, val, SingleWidth); -} - -Fault -RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width) -{ - return floatRegFile.setReg(floatReg, val, width); + return floatRegFile.setReg(floatReg, val); } Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) { - return floatRegFile.setRegBits(floatReg, val, SingleWidth); -} - -Fault -RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - return floatRegFile.setRegBits(floatReg, val, width); + return floatRegFile.setRegBits(floatReg, val); } void diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index b05f513b4..55b22638b 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -66,14 +66,10 @@ namespace MipsISA Fault setIntReg(int intReg, const IntReg &val); - FloatRegVal readFloatReg(int floatReg); - FloatRegVal readFloatReg(int floatReg, int width); + FloatReg readFloatReg(int floatReg); FloatRegBits readFloatRegBits(int floatReg); - FloatRegBits readFloatRegBits(int floatReg, int width); - Fault setFloatReg(int floatReg, const FloatRegVal &val); - Fault setFloatReg(int floatReg, const FloatRegVal &val, int width); + Fault setFloatReg(int floatReg, const FloatReg &val); Fault setFloatRegBits(int floatReg, const FloatRegBits &val); - Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width); void setShadowSet(int css); diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh index 4e0684e78..e38e80975 100644 --- a/src/arch/mips/types.hh +++ b/src/arch/mips/types.hh @@ -44,12 +44,8 @@ namespace MipsISA // floating point register file entry type - typedef uint32_t FloatReg32; - typedef uint64_t FloatReg64; - typedef uint64_t FloatRegBits; - - typedef double FloatRegVal; - typedef double FloatReg; + typedef uint32_t FloatRegBits; + typedef float FloatReg; // cop-0/cop-1 system control register typedef uint64_t MiscReg; diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc index 2d1af2218..6fdc36489 100644 --- a/src/arch/sparc/floatregfile.cc +++ b/src/arch/sparc/floatregfile.cc @@ -43,155 +43,38 @@ class Checkpoint; void FloatRegFile::clear() { - memset(regSpace, 0, sizeof(regSpace)); + memset(regs.q, 0, sizeof(regs.q)); } -FloatReg FloatRegFile::readReg(int floatReg, int width) +FloatReg FloatRegFile::readReg(int floatReg) { - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - FloatReg result; - switch(width) - { - case SingleWidth: - uint32_t result32; - float32_t fresult32; - memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); - result32 = htog(result32); - memcpy(&fresult32, &result32, sizeof(result32)); - result = fresult32; - DPRINTF(FloatRegs, "Read FP32 register %d = [%f]0x%x\n", - floatReg, result, result32); - break; - case DoubleWidth: - uint64_t result64; - float64_t fresult64; - memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); - result64 = htog(result64); - memcpy(&fresult64, &result64, sizeof(result64)); - result = fresult64; - DPRINTF(FloatRegs, "Read FP64 register %d = [%f]0x%x\n", - floatReg, result, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return result; + return regs.s[floatReg]; } -FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) +FloatRegBits FloatRegFile::readRegBits(int floatReg) { - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - FloatRegBits result; - switch(width) - { - case SingleWidth: - uint32_t result32; - memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); - result = htog(result32); - DPRINTF(FloatRegs, "Read FP32 bits register %d = 0x%x\n", - floatReg, result); - break; - case DoubleWidth: - uint64_t result64; - memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); - result = htog(result64); - DPRINTF(FloatRegs, "Read FP64 bits register %d = 0x%x\n", - floatReg, result); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return result; + return regs.q[floatReg]; } -Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) +Fault FloatRegFile::setReg(int floatReg, const FloatReg &val) { - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - - uint32_t result32; - uint64_t result64; - float32_t fresult32; - float64_t fresult64; - switch(width) - { - case SingleWidth: - fresult32 = val; - memcpy(&result32, &fresult32, sizeof(result32)); - result32 = gtoh(result32); - memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); - DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n", - floatReg, result32); - break; - case DoubleWidth: - fresult64 = val; - memcpy(&result64, &fresult64, sizeof(result64)); - result64 = gtoh(result64); - memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); - DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n", - floatReg, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } + regs.s[floatReg] = val; return NoFault; } -Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) +Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val) { - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - uint32_t result32; - uint64_t result64; - switch(width) - { - case SingleWidth: - result32 = gtoh((uint32_t)val); - memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); - DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n", - floatReg, result32); - break; - case DoubleWidth: - result64 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); - DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n", - floatReg, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } + regs.q[floatReg] = val; return NoFault; } void FloatRegFile::serialize(std::ostream &os) { - uint8_t *float_reg = (uint8_t*)regSpace; - SERIALIZE_ARRAY(float_reg, - SingleWidth / 8 * NumFloatRegs); + SERIALIZE_ARRAY(regs.q, NumFloatRegs); } void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) { - uint8_t *float_reg = (uint8_t*)regSpace; - UNSERIALIZE_ARRAY(float_reg, - SingleWidth / 8 * NumFloatRegs); + UNSERIALIZE_ARRAY(regs.q, NumFloatRegs); } diff --git a/src/arch/sparc/floatregfile.hh b/src/arch/sparc/floatregfile.hh index 265e71b4a..d1ac39842 100644 --- a/src/arch/sparc/floatregfile.hh +++ b/src/arch/sparc/floatregfile.hh @@ -45,37 +45,25 @@ namespace SparcISA const int NumFloatArchRegs = 64; const int NumFloatRegs = 64; - typedef float float32_t; - typedef double float64_t; - //FIXME long double refers to a 10 byte float, rather than a - //16 byte float as required. This data type may have to be emulated. - typedef double float128_t; - class FloatRegFile { - public: - static const int SingleWidth = 32; - static const int DoubleWidth = 64; - static const int QuadWidth = 128; - protected: - - //Since the floating point registers overlap each other, - //A generic storage space is used. The float to be returned is - //pulled from the appropriate section of this region. - char regSpace[(SingleWidth / 8) * NumFloatRegs]; + union { + uint32_t q[NumFloatRegs]; + float s[NumFloatRegs]; + } regs; public: void clear(); - FloatReg readReg(int floatReg, int width); + FloatReg readReg(int floatReg); - FloatRegBits readRegBits(int floatReg, int width); + FloatRegBits readRegBits(int floatReg); - Fault setReg(int floatReg, const FloatReg &val, int width); + Fault setReg(int floatReg, const FloatReg &val); - Fault setRegBits(int floatReg, const FloatRegBits &val, int width); + Fault setRegBits(int floatReg, const FloatRegBits &val); void serialize(std::ostream &os); diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 1daa43818..287516f9a 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -74,49 +74,24 @@ void RegFile::clear() intRegFile.clear(); } -FloatReg RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg, width); -} - FloatReg RegFile::readFloatReg(int floatReg) { - //Use the "natural" width of a single float - return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg, width); + return floatRegFile.readReg(floatReg); } FloatRegBits RegFile::readFloatRegBits(int floatReg) { - //Use the "natural" width of a single float - return floatRegFile.readRegBits(floatReg, - FloatRegFile::SingleWidth); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width) -{ - floatRegFile.setReg(floatReg, val, width); + return floatRegFile.readRegBits(floatReg); } void RegFile::setFloatReg(int floatReg, const FloatReg &val) { - //Use the "natural" width of a single float - setFloatReg(floatReg, val, FloatRegFile::SingleWidth); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - floatRegFile.setRegBits(floatReg, val, width); + floatRegFile.setReg(floatReg, val); } void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) { - //Use the "natural" width of a single float - floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth); + floatRegFile.setRegBits(floatReg, val); } IntReg RegFile::readIntReg(int intReg) diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 2333d9da5..a9d9be200 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -70,20 +70,12 @@ namespace SparcISA void clear(); - FloatReg readFloatReg(int floatReg, int width); - FloatReg readFloatReg(int floatReg); - FloatRegBits readFloatRegBits(int floatReg, int width); - FloatRegBits readFloatRegBits(int floatReg); - void setFloatReg(int floatReg, const FloatReg &val, int width); - void setFloatReg(int floatReg, const FloatReg &val); - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - void setFloatRegBits(int floatReg, const FloatRegBits &val); IntReg readIntReg(int intReg); diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh index 501e2e8cb..c7ece9dfa 100644 --- a/src/arch/sparc/types.hh +++ b/src/arch/sparc/types.hh @@ -42,8 +42,8 @@ namespace SparcISA typedef uint64_t IntReg; typedef Twin64_t LargestRead; typedef uint64_t MiscReg; - typedef double FloatReg; - typedef uint64_t FloatRegBits; + typedef float FloatReg; + typedef uint32_t FloatRegBits; typedef union { IntReg intReg; diff --git a/src/arch/x86/floatregfile.cc b/src/arch/x86/floatregfile.cc index fce7f4868..bbdf1d5c1 100644 --- a/src/arch/x86/floatregfile.cc +++ b/src/arch/x86/floatregfile.cc @@ -101,28 +101,28 @@ void FloatRegFile::clear() memset(q, 0, sizeof(FloatReg) * NumFloatRegs); } -FloatReg FloatRegFile::readReg(int floatReg, int width) +FloatReg FloatRegFile::readReg(int floatReg) { FloatReg reg = d[floatReg]; DPRINTF(FloatRegs, "Reading %f from register %d.\n", reg, floatReg); return reg; } -FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) +FloatRegBits FloatRegFile::readRegBits(int floatReg) { FloatRegBits reg = q[floatReg]; DPRINTF(FloatRegs, "Reading %#x from register %d.\n", reg, floatReg); return reg; } -Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) +Fault FloatRegFile::setReg(int floatReg, const FloatReg &val) { DPRINTF(FloatRegs, "Writing %f to register %d.\n", val, floatReg); d[floatReg] = val; return NoFault; } -Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) +Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val) { DPRINTF(FloatRegs, "Writing bits %#x to register %d.\n", val, floatReg); q[floatReg] = val; diff --git a/src/arch/x86/floatregfile.hh b/src/arch/x86/floatregfile.hh index ab239dd7d..aeed5bfa0 100644 --- a/src/arch/x86/floatregfile.hh +++ b/src/arch/x86/floatregfile.hh @@ -105,29 +105,23 @@ namespace X86ISA class FloatRegFile { - public: - static const int SingleWidth = 32; - static const int DoubleWidth = 64; - static const int QuadWidth = 128; - protected: union { uint64_t q[NumFloatRegs]; double d[NumFloatRegs]; - float f[NumFloatRegs][2]; }; public: void clear(); - FloatReg readReg(int floatReg, int width); + FloatReg readReg(int floatReg); - FloatRegBits readRegBits(int floatReg, int width); + FloatRegBits readRegBits(int floatReg); - Fault setReg(int floatReg, const FloatReg &val, int width); + Fault setReg(int floatReg, const FloatReg &val); - Fault setRegBits(int floatReg, const FloatRegBits &val, int width); + Fault setRegBits(int floatReg, const FloatRegBits &val); void serialize(std::ostream &os); diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc index f6a9c1480..17b7a12d1 100644 --- a/src/arch/x86/regfile.cc +++ b/src/arch/x86/regfile.cc @@ -133,49 +133,24 @@ void RegFile::clear() intRegFile.clear(); } -FloatReg RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg, width); -} - FloatReg RegFile::readFloatReg(int floatReg) { - //Use the "natural" width of a single float - return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg, width); + return floatRegFile.readReg(floatReg); } FloatRegBits RegFile::readFloatRegBits(int floatReg) { - //Use the "natural width of a single float - return floatRegFile.readRegBits(floatReg, - FloatRegFile::SingleWidth); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width) -{ - floatRegFile.setReg(floatReg, val, width); + return floatRegFile.readRegBits(floatReg); } void RegFile::setFloatReg(int floatReg, const FloatReg &val) { - //Use the "natural" width of a single float - setFloatReg(floatReg, val, FloatRegFile::SingleWidth); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - floatRegFile.setRegBits(floatReg, val, width); + floatRegFile.setReg(floatReg, val); } void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) { - //Use the "natural" width of a single float - floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth); + floatRegFile.setRegBits(floatReg, val); } IntReg RegFile::readIntReg(int intReg) diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh index 0414622a2..e9e96c4f8 100644 --- a/src/arch/x86/regfile.hh +++ b/src/arch/x86/regfile.hh @@ -99,20 +99,12 @@ namespace X86ISA void clear(); - FloatReg readFloatReg(int floatReg, int width); - FloatReg readFloatReg(int floatReg); - FloatRegBits readFloatRegBits(int floatReg, int width); - FloatRegBits readFloatRegBits(int floatReg); - void setFloatReg(int floatReg, const FloatReg &val, int width); - void setFloatReg(int floatReg, const FloatReg &val); - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - void setFloatRegBits(int floatReg, const FloatRegBits &val); IntReg readIntReg(int intReg); -- cgit v1.2.3