From 326191adc9ed16c672a7f2442055dc8a23626739 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 23 Feb 2011 15:10:49 -0600
Subject: ARM: Squash state on FPSCR stride or len write.

---
 src/arch/arm/isa/insts/fp.isa | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/arch')

diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 961b9a355..4911d50f1 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -209,7 +209,8 @@ let {{
                                  { "code": vmsrFpscrCode,
                                    "predicate_test": predicateTest,
                                    "op_class": "SimdFloatMiscOp" },
-                                 ["IsSerializeAfter","IsNonSpeculative"])
+                                 ["IsSerializeAfter","IsNonSpeculative",
+                                  "IsSquashAfter"])
     header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
     decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
     exec_output += PredOpExecute.subst(vmsrFpscrIop);
-- 
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