From 4d5f2c28a88f83d390e80407f55a8a02ead33878 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 22 Oct 2011 22:30:07 -0700 Subject: syscall_emul: implement MAP_FIXED option to mmap() --- src/arch/alpha/linux/linux.hh | 1 + src/arch/alpha/tru64/tru64.hh | 1 + src/arch/arm/linux/linux.hh | 1 + src/arch/mips/linux/linux.hh | 1 + src/arch/power/linux/linux.hh | 1 + src/arch/sparc/linux/linux.hh | 1 + src/arch/sparc/solaris/solaris.hh | 1 + src/arch/x86/linux/linux.hh | 2 ++ 8 files changed, 9 insertions(+) (limited to 'src/arch') diff --git a/src/arch/alpha/linux/linux.hh b/src/arch/alpha/linux/linux.hh index c728ce1fb..3304816c3 100644 --- a/src/arch/alpha/linux/linux.hh +++ b/src/arch/alpha/linux/linux.hh @@ -69,6 +69,7 @@ class AlphaLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x10; + static const unsigned TGT_MAP_FIXED = 0x100; //@{ /// For getsysinfo(). diff --git a/src/arch/alpha/tru64/tru64.hh b/src/arch/alpha/tru64/tru64.hh index 0ee12973c..f0cad8289 100644 --- a/src/arch/alpha/tru64/tru64.hh +++ b/src/arch/alpha/tru64/tru64.hh @@ -64,6 +64,7 @@ class AlphaTru64 : public Tru64 /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x10; + static const unsigned TGT_MAP_FIXED = 0x100; //@{ /// For getsysinfo(). diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh index 33e48fc93..40d586aaf 100644 --- a/src/arch/arm/linux/linux.hh +++ b/src/arch/arm/linux/linux.hh @@ -91,6 +91,7 @@ class ArmLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// For getrusage(). diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh index a2418cfb6..949cce8aa 100644 --- a/src/arch/mips/linux/linux.hh +++ b/src/arch/mips/linux/linux.hh @@ -65,6 +65,7 @@ class MipsLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x800; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// For getsysinfo(). diff --git a/src/arch/power/linux/linux.hh b/src/arch/power/linux/linux.hh index 1bfc9cbd8..45ca048a0 100644 --- a/src/arch/power/linux/linux.hh +++ b/src/arch/power/linux/linux.hh @@ -127,6 +127,7 @@ class PowerLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// ioctl() command codes. diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh index 1f7567d43..8ac408812 100644 --- a/src/arch/sparc/linux/linux.hh +++ b/src/arch/sparc/linux/linux.hh @@ -77,6 +77,7 @@ class SparcLinux : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { int64_t uptime; /* Seconds since boot */ diff --git a/src/arch/sparc/solaris/solaris.hh b/src/arch/sparc/solaris/solaris.hh index df2565027..8222addab 100644 --- a/src/arch/sparc/solaris/solaris.hh +++ b/src/arch/sparc/solaris/solaris.hh @@ -59,6 +59,7 @@ class SparcSolaris : public Solaris static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x100; + static const unsigned TGT_MAP_FIXED = 0x10; }; #endif diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh index 99b09f405..4e5d43d45 100644 --- a/src/arch/x86/linux/linux.hh +++ b/src/arch/x86/linux/linux.hh @@ -88,6 +88,7 @@ class X86Linux64 : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { uint64_t iov_base; // void * @@ -158,6 +159,7 @@ class X86Linux32 : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { int32_t uptime; /* Seconds since boot */ -- cgit v1.2.3 From 6f9d294e8685f49d91af48065736ac1d67e53718 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 22 Oct 2011 22:30:08 -0700 Subject: SE: move page allocation from PageTable to Process PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable. The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process. --- src/arch/alpha/process.cc | 2 +- src/arch/arm/linux/process.cc | 2 +- src/arch/arm/process.cc | 3 +-- src/arch/mips/process.cc | 2 +- src/arch/power/process.cc | 3 +-- src/arch/sparc/process.cc | 3 +-- src/arch/x86/process.cc | 9 ++++----- 7 files changed, 10 insertions(+), 14 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 637fbe065..4a3079264 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -126,7 +126,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize) stack_min = roundDown(stack_min, pageSize); stack_size = stack_base - stack_min; // map memory - pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + allocateMem(stack_min, roundUp(stack_size, pageSize)); // map out initial stack contents Addr argv_array_base = stack_min + intSize; // room for argc diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index f17749252..c65962d00 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -503,7 +503,7 @@ void ArmLinuxProcess::initState() { ArmLiveProcess::initState(); - pTable->allocate(commPage, PageBytes); + allocateMem(commPage, PageBytes); ThreadContext *tc = system->getThreadContext(contextIds[0]); uint8_t swiNeg1[] = { diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index c3b02744e..aa5d7dfce 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -251,8 +251,7 @@ ArmLiveProcess::argsInit(int intSize, int pageSize) stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents uint32_t sentry_base = stack_base - sentry_size; diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index c62b60b98..5643ff18a 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -136,7 +136,7 @@ MipsLiveProcess::argsInit(int pageSize) stack_min = roundDown(stack_min, pageSize); stack_size = stack_base - stack_min; // map memory - pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + allocateMem(stack_min, roundUp(stack_size, pageSize)); // map out initial stack contents IntType argv_array_base = stack_min + intSize; // room for argc diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc index d12e3eab6..788c7cc0c 100644 --- a/src/arch/power/process.cc +++ b/src/arch/power/process.cc @@ -187,8 +187,7 @@ PowerLiveProcess::argsInit(int intSize, int pageSize) stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents uint32_t sentry_base = stack_base - sentry_size; diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 3eee3d137..5c594dcbc 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -316,8 +316,7 @@ SparcLiveProcess::argsInit(int pageSize) stack_size = stack_base - stack_min; // Allocate space for the stack - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents IntType sentry_base = stack_base - sentry_size; diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 79a140776..f5ba787c9 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -167,7 +167,7 @@ X86_64LiveProcess::initState() argsInit(sizeof(uint64_t), VMPageSize); // Set up the vsyscall page for this process. - pTable->allocate(vsyscallPage.base, vsyscallPage.size); + allocateMem(vsyscallPage.base, vsyscallPage.size); uint8_t vtimeBlob[] = { 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 0x0f,0x05, // syscall @@ -265,7 +265,7 @@ I386LiveProcess::initState() * Set up a GDT for this process. The whole GDT wouldn't really be for * this process, but the only parts we care about are. */ - pTable->allocate(_gdtStart, _gdtSize); + allocateMem(_gdtStart, _gdtSize); uint64_t zero = 0; assert(_gdtSize % sizeof(zero) == 0); for (Addr gdtCurrent = _gdtStart; @@ -274,7 +274,7 @@ I386LiveProcess::initState() } // Set up the vsyscall page for this process. - pTable->allocate(vsyscallPage.base, vsyscallPage.size); + allocateMem(vsyscallPage.base, vsyscallPage.size); uint8_t vsyscallBlob[] = { 0x51, // push %ecx 0x52, // push %edp @@ -577,8 +577,7 @@ X86LiveProcess::argsInit(int pageSize, stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents IntType sentry_base = stack_base - sentry_size; -- cgit v1.2.3 From d735abe5dabf483aafb0ccfb0a70cb7c3b0a5a74 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 31 Oct 2011 01:09:44 -0700 Subject: GCC: Get everything working with gcc 4.6.1. And by "everything" I mean all the quick regressions. --- src/arch/alpha/ev5.cc | 7 ++----- src/arch/alpha/isa/mem.isa | 2 +- src/arch/arm/isa/formats/fp.isa | 18 ++++++++++-------- src/arch/arm/isa/insts/fp.isa | 4 ++-- src/arch/arm/isa/insts/m5ops.isa | 19 +++---------------- src/arch/arm/isa/insts/macromem.isa | 7 ++++--- src/arch/arm/isa/insts/neon.isa | 16 +++++++--------- src/arch/arm/isa/templates/mem.isa | 4 ++-- src/arch/mips/isa/decoder.isa | 8 +++----- src/arch/mips/isa/formats/mt.isa | 22 ++++++---------------- src/arch/mips/isa/includes.isa | 2 ++ src/arch/mips/tlb.cc | 2 -- src/arch/power/isa/formats/mem.isa | 2 +- src/arch/power/tlb.cc | 2 -- src/arch/sparc/isa/formats/mem/util.isa | 5 ++--- src/arch/x86/isa/microops/base.isa | 3 ++- 16 files changed, 47 insertions(+), 76 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 2bc913f92..6259f8fc2 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -209,8 +209,6 @@ int break_ipl = -1; void ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) { - uint64_t old; - if (tc->misspeculating()) return; @@ -262,12 +260,11 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) case IPR_PALtemp23: // write entire quad w/ no side-effect - old = ipr[idx]; - ipr[idx] = val; #if FULL_SYSTEM if (tc->getKernelStats()) - tc->getKernelStats()->context(old, val, tc); + tc->getKernelStats()->context(ipr[idx], val, tc); #endif + ipr[idx] = val; break; case IPR_DTB_PTE: diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index ed5128204..f286be91c 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -388,7 +388,7 @@ def template MiscExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; + Addr EA M5_VAR_USED; Fault fault = NoFault; %(fp_enable_check)s; diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 812338c30..0cb27d7f1 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -561,20 +561,22 @@ let {{ } } case 0xa: + if (q) + return new Unknown(machInst); if (b) { - return decodeNeonUSThreeReg( - q, u, size, machInst, vd, vn, vm); + return decodeNeonUSThreeUSReg( + u, size, machInst, vd, vn, vm); } else { - return decodeNeonUSThreeReg( - q, u, size, machInst, vd, vn, vm); + return decodeNeonUSThreeUSReg( + u, size, machInst, vd, vn, vm); } case 0xb: if (b) { - if (u) { + if (u || q) { return new Unknown(machInst); } else { - return decodeNeonUThreeReg( - q, size, machInst, vd, vn, vm); + return decodeNeonUThreeUSReg( + size, machInst, vd, vn, vm); } } else { if (u) { @@ -1542,7 +1544,7 @@ let {{ else return new NVswpD(machInst, vd, vm); case 0x1: - return decodeNeonUTwoMiscReg( + return decodeNeonUTwoMiscSReg( q, size, machInst, vd, vm); case 0x2: return decodeNeonUTwoMiscReg( diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index f82858bbd..b701995f4 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -447,7 +447,7 @@ let {{ exec_output = "" singleSimpleCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = (FPSCR) FpscrExc; + FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; FpDest = %(op)s; ''' singleCode = singleSimpleCode + ''' @@ -457,7 +457,7 @@ let {{ "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" doubleCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = (FPSCR) FpscrExc; + FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; double dest = %(op)s; FpDestP0_uw = dblLow(dest); FpDestP1_uw = dblHi(dest); diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index e891a0a91..3b837cba9 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -54,9 +54,7 @@ let {{ armCode = ''' -#if FULL_SYSTEM PseudoInst::arm(xc->tcBase()); -#endif ''' armIop = InstObjParams("arm", "Arm", "PredOp", { "code": armCode, @@ -67,9 +65,7 @@ let {{ exec_output += PredOpExecute.subst(armIop) quiesceCode = ''' -#if FULL_SYSTEM PseudoInst::quiesce(xc->tcBase()); -#endif ''' quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", { "code": quiesceCode, @@ -80,9 +76,7 @@ let {{ exec_output += QuiescePredOpExecute.subst(quiesceIop) quiesceNsCode = ''' -#if FULL_SYSTEM PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); -#endif ''' quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", @@ -94,9 +88,7 @@ let {{ exec_output += QuiescePredOpExecute.subst(quiesceNsIop) quiesceCyclesCode = ''' -#if FULL_SYSTEM PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); -#endif ''' quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", @@ -108,11 +100,9 @@ let {{ exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) quiesceTimeCode = ''' -#if FULL_SYSTEM uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); R0 = bits(qt_val, 31, 0); R1 = bits(qt_val, 63, 32); -#endif ''' quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", @@ -188,9 +178,7 @@ let {{ exec_output += PredOpExecute.subst(m5exitIop) loadsymbolCode = ''' -#if FULL_SYSTEM PseudoInst::loadsymbol(xc->tcBase()); -#endif ''' loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", @@ -204,6 +192,9 @@ let {{ initparamCode = ''' #if FULL_SYSTEM Rt = PseudoInst::initParam(xc->tcBase()); +#else + PseudoInst::panicFsOnlyPseudoInst("initparam"); + Rt = 0; #endif ''' @@ -260,11 +251,9 @@ let {{ exec_output += PredOpExecute.subst(m5checkpointIop) m5readfileCode = ''' -#if FULL_SYSTEM int n = 4; uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset); -#endif ''' m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", { "code": m5readfileCode, @@ -291,9 +280,7 @@ let {{ exec_output += PredOpExecute.subst(m5switchcpuIop) m5addsymbolCode = ''' -#if FULL_SYSTEM PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); -#endif ''' m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", { "code": m5addsymbolCode, diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 815d4c258..db36a3fff 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -563,15 +563,16 @@ let {{ let {{ exec_output = '' - for type in ('uint8_t', 'uint16_t', 'uint32_t'): + for typeSize in (8, 16, 32): for sRegs in 1, 2: - for dRegs in range(sRegs, 5): + for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)): for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop", "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop", "MicroPackNeon%(dRegs)dto%(sRegs)dUop"): Name = format % { "sRegs" : sRegs * 2, "dRegs" : dRegs * 2 } - substDict = { "class_name" : Name, "targs" : type } + substDict = { "class_name" : Name, + "targs" : "uint%d_t" % typeSize } exec_output += MicroNeonExecDeclare.subst(substDict) }}; diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index fdb6237c0..dd0d49a5c 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1619,10 +1619,8 @@ let {{ threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode) threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode) - threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes, + threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes, 2, vaddCode, pairwise=True) - threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes, - 4, vaddCode, pairwise=True) vaddlwCode = ''' destElem = (BigElement)srcElem1 + (BigElement)srcElem2; ''' @@ -2113,11 +2111,9 @@ let {{ ''' threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode) - threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True) - threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True) + threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True) - threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True) - threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True) + threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True) vqdmulhCode = ''' FPSCR fpscr = (FPSCR) FpscrQc; @@ -3140,8 +3136,10 @@ let {{ destReg.elements[i + 1] = mid; } ''' - twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode) - twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode) + twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", + smallUnsignedTypes, 2, vtrnCode) + twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", + smallUnsignedTypes, 4, vtrnCode) vuzpCode = ''' Element mid[eCount]; diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index a00114409..a4a740f89 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -1112,7 +1112,7 @@ def template LoadRegConstructor {{ (IntRegIndex)_index) { %(constructor)s; - bool conditional = false; + bool conditional M5_VAR_USED = false; if (!(condCode == COND_AL || condCode == COND_UC)) { conditional = true; for (int x = 0; x < _numDestRegs; x++) { @@ -1166,7 +1166,7 @@ def template LoadImmConstructor {{ (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) { %(constructor)s; - bool conditional = false; + bool conditional M5_VAR_USED = false; if (!(condCode == COND_AL || condCode == COND_UC)) { conditional = true; for (int x = 0; x < _numDestRegs; x++) { diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 7b8dafdba..179e409dd 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -497,8 +497,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + FP_Base_DepTag); - data = insertBits(data, top_bit, - bottom_bit, Rt); + data = insertBits(data, MT_H ? 63 : 31, + MT_H ? 32 : 0, Rt); xc->setRegOtherThread(RD + FP_Base_DepTag, data); }}); @@ -532,7 +532,7 @@ decode OPCODE_HI default Unknown::unknown() { panic("FP Control Value (%d) " "Not Available. Ignoring " "Access to Floating Control " - "Status Register", FS); + "S""tatus Register", FS); } xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); }}); @@ -776,7 +776,6 @@ decode OPCODE_HI default Unknown::unknown() { bits(pageGrain, pageGrain.esp) == 1) { SP = 1; } - IndexReg index = Index; Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); }}); 0x06: tlbwr({{ @@ -842,7 +841,6 @@ decode OPCODE_HI default Unknown::unknown() { bits(pageGrain, pageGrain.esp) == 1) { SP = 1; } - IndexReg index = Index; Ptr->insertAt(newEntry, Random, SP); }}); diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 1944d69d3..41f94e129 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -107,7 +107,7 @@ def template ThreadRegisterExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - int64_t data; + int64_t data M5_VAR_USED; %(op_decl)s; %(op_rd)s; @@ -126,17 +126,6 @@ def template ThreadRegisterExecute {{ } else if (vpeControl.targTC > mvpConf0.ptc) { data = -1; } else { - int top_bit = 0; - int bottom_bit = 0; - - if (MT_H == 1) { - top_bit = 63; - bottom_bit = 32; - } else { - top_bit = 31; - bottom_bit = 0; - } - %(code)s; } } else { @@ -203,10 +192,11 @@ def format MT_MFTR(code, *flags) {{ flags += ('IsNonSpeculative', ) # code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code - code += 'if (MT_H == 1) {\n' - code += 'data = bits(data, top_bit, bottom_bit);\n' - code += '}\n' - code += 'Rd = data;\n' + code += ''' + if (MT_H) + data = bits(data, 63, 32); + Rd = data; + ''' iop = InstObjParams(name, Name, 'MTOp', code, flags) header_output = BasicDeclare.subst(iop) diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index c9f5da41d..4ce03b1c2 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -52,7 +52,9 @@ output decoder {{ #include "arch/mips/faults.hh" #include "arch/mips/isa_traits.hh" #include "arch/mips/mt_constants.hh" +#include "arch/mips/pagetable.hh" #include "arch/mips/pra_constants.hh" +#include "arch/mips/tlb.hh" #include "arch/mips/utility.hh" #include "base/loader/symtab.hh" #include "base/cprintf.hh" diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index e35ac6d4a..57d8849e1 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -129,7 +129,6 @@ int TLB::probeEntry(Addr vpn, uint8_t asn) const { // assume not found... - PTE *retval = NULL; int Ind = -1; PageTable::const_iterator i = lookupTable.find(vpn); if (i != lookupTable.end()) { @@ -144,7 +143,6 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const if (((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) { // We have a VPN + ASID Match - retval = pte; Ind = index; break; } diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index 0361ee998..a409eefac 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -123,7 +123,7 @@ def template LoadCompleteAcc {{ %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; + Addr M5_VAR_USED EA; Fault fault = NoFault; %(op_decl)s; diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc index 8a088032c..0b3edd5a2 100644 --- a/src/arch/power/tlb.cc +++ b/src/arch/power/tlb.cc @@ -118,7 +118,6 @@ int TLB::probeEntry(Addr vpn,uint8_t asn) const { // assume not found... - PowerISA::PTE *retval = NULL; int Ind = -1; PageTable::const_iterator i = lookupTable.find(vpn); if (i != lookupTable.end()) { @@ -132,7 +131,6 @@ TLB::probeEntry(Addr vpn,uint8_t asn) const && (pte->G || (asn == pte->asid))) { // We have a VPN + ASID Match - retval = pte; Ind = index; break; } diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 06206c02b..0ca56252e 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -326,9 +326,8 @@ let {{ ''' TruncateEA = ''' -#if !FULL_SYSTEM - EA = Pstate<3:> ? EA<31:0> : EA; -#endif + if (!FULL_SYSTEM) + EA = Pstate<3:> ? EA<31:0> : EA; ''' }}; diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index 664f91860..5798ac4b0 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -59,7 +59,8 @@ let {{ ''' + generatorNameTemplate + '''(StaticInstPtr curMacroop) { static const char *macrocodeBlock = romMnemonic; - static const ExtMachInst dummyExtMachInst; + static const ExtMachInst dummyExtMachInst = \ + X86ISA::NoopMachInst; static const EmulEnv dummyEmulEnv(0, 0, 1, 1, 1); Macroop * macroop = dynamic_cast(curMacroop.get()); -- cgit v1.2.3 From 582ea4d5431f9fa9edbeb16835b04171647ea18b Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Thu, 3 Nov 2011 22:52:21 -0500 Subject: x86: Add microop for fence This patch adds a new microop for memory barrier. The microop itself does nothing, but since it is marked as a memory barrier, the O3 CPU should flush all the pending loads and stores before the fence to the memory system. --- .../general_purpose/arithmetic/add_and_subtract.py | 36 +++++++++++++++ .../arithmetic/increment_and_decrement.py | 8 ++++ .../general_purpose/compare_and_test/bit_test.py | 24 ++++++++++ .../insts/general_purpose/data_transfer/xchg.py | 12 +++++ src/arch/x86/isa/insts/general_purpose/logical.py | 28 ++++++++++++ .../x86/isa/insts/general_purpose/semaphores.py | 8 ++++ src/arch/x86/isa/microops/specop.isa | 53 ++++++++++++++++++++++ 7 files changed, 169 insertions(+) (limited to 'src/arch') diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py index 9fc3e9035..68031c76c 100644 --- a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py @@ -67,18 +67,22 @@ def macroop ADD_P_I def macroop ADD_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop ADD_LOCKED_P_I { rdip t7 limm t2, imm + mfence ldstl t1, seg, riprel, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADD_M_R @@ -98,17 +102,21 @@ def macroop ADD_P_R def macroop ADD_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop ADD_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADD_R_M @@ -168,18 +176,22 @@ def macroop SUB_P_I def macroop SUB_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop SUB_LOCKED_P_I { rdip t7 limm t2, imm + mfence ldstl t1, seg, riprel, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop SUB_M_R @@ -199,17 +211,21 @@ def macroop SUB_P_R def macroop SUB_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop SUB_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADC_R_R @@ -243,18 +259,22 @@ def macroop ADC_P_I def macroop ADC_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop ADC_LOCKED_P_I { rdip t7 limm t2, imm + mfence ldstl t1, seg, riprel, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADC_M_R @@ -274,17 +294,21 @@ def macroop ADC_P_R def macroop ADC_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop ADC_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADC_R_M @@ -344,18 +368,22 @@ def macroop SBB_P_I def macroop SBB_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop SBB_LOCKED_P_I { rdip t7 limm t2, imm + mfence ldstl t1, seg, riprel, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop SBB_M_R @@ -375,17 +403,21 @@ def macroop SBB_P_R def macroop SBB_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop SBB_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop NEG_R @@ -410,16 +442,20 @@ def macroop NEG_P def macroop NEG_LOCKED_M { + mfence ldstl t1, seg, sib, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) stul t1, seg, sib, disp + mfence }; def macroop NEG_LOCKED_P { rdip t7 + mfence ldstl t1, seg, riprel, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) stul t1, seg, riprel, disp + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py index f27cd7008..515082d64 100644 --- a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py @@ -58,17 +58,21 @@ def macroop INC_P def macroop INC_LOCKED_M { + mfence ldstl t1, seg, sib, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) stul t1, seg, sib, disp + mfence }; def macroop INC_LOCKED_P { rdip t7 + mfence ldstl t1, seg, riprel, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) stul t1, seg, riprel, disp + mfence }; def macroop DEC_R @@ -93,16 +97,20 @@ def macroop DEC_P def macroop DEC_LOCKED_M { + mfence ldstl t1, seg, sib, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) stul t1, seg, sib, disp + mfence }; def macroop DEC_LOCKED_P { rdip t7 + mfence ldstl t1, seg, riprel, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) stul t1, seg, riprel, disp + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py index 66eb0f8a2..f69e1dc48 100644 --- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py @@ -114,10 +114,12 @@ def macroop BTC_LOCKED_M_I { limm t1, imm, dataSize=asz limm t4, 1 roli t4, t4, imm + mfence ldstl t1, seg, sib, disp sexti t0, t1, imm, flags=(CF,) xor t1, t1, t4 stul t1, seg, sib, disp + mfence }; def macroop BTC_LOCKED_P_I { @@ -125,10 +127,12 @@ def macroop BTC_LOCKED_P_I { limm t1, imm, dataSize=asz limm t4, 1 roli t4, t4, imm + mfence ldstl t1, seg, riprel, disp sexti t0, t1, imm, flags=(CF,) xor t1, t1, t4 stul t1, seg, riprel, disp + mfence }; def macroop BTC_R_R { @@ -168,10 +172,12 @@ def macroop BTC_LOCKED_M_R { lea t3, flatseg, [dsz, t3, base], dataSize=asz limm t4, 1 rol t4, t4, reg + mfence ldstl t1, seg, [scale, index, t3], disp sext t0, t1, reg, flags=(CF,) xor t1, t1, t4 stul t1, seg, [scale, index, t3], disp + mfence }; def macroop BTC_LOCKED_P_R { @@ -180,10 +186,12 @@ def macroop BTC_LOCKED_P_R { srai t3, t2, ldsz, dataSize=asz limm t4, 1 rol t4, t4, reg + mfence ldstl t1, seg, [dsz, t3, t7], disp sext t0, t1, reg, flags=(CF,) xor t1, t1, t4 stul t1, seg, [dsz, t3, t7], disp + mfence }; def macroop BTR_R_I { @@ -218,10 +226,12 @@ def macroop BTR_LOCKED_M_I { limm t1, imm, dataSize=asz limm t4, "(uint64_t(-(2ULL)))" roli t4, t4, imm + mfence ldstl t1, seg, sib, disp sexti t0, t1, imm, flags=(CF,) and t1, t1, t4 stul t1, seg, sib, disp + mfence }; def macroop BTR_LOCKED_P_I { @@ -229,10 +239,12 @@ def macroop BTR_LOCKED_P_I { limm t1, imm, dataSize=asz limm t4, "(uint64_t(-(2ULL)))" roli t4, t4, imm + mfence ldstl t1, seg, riprel, disp sexti t0, t1, imm, flags=(CF,) and t1, t1, t4 stul t1, seg, riprel, disp + mfence }; def macroop BTR_R_R { @@ -272,10 +284,12 @@ def macroop BTR_LOCKED_M_R { lea t3, flatseg, [dsz, t3, base], dataSize=asz limm t4, "(uint64_t(-(2ULL)))" rol t4, t4, reg + mfence ldstl t1, seg, [scale, index, t3], disp sext t0, t1, reg, flags=(CF,) and t1, t1, t4 stul t1, seg, [scale, index, t3], disp + mfence }; def macroop BTR_LOCKED_P_R { @@ -284,10 +298,12 @@ def macroop BTR_LOCKED_P_R { srai t3, t2, ldsz, dataSize=asz limm t4, "(uint64_t(-(2ULL)))" rol t4, t4, reg + mfence ldstl t1, seg, [dsz, t3, t7], disp sext t0, t1, reg, flags=(CF,) and t1, t1, t4 stul t1, seg, [dsz, t3, t7], disp + mfence }; def macroop BTS_R_I { @@ -322,10 +338,12 @@ def macroop BTS_LOCKED_M_I { limm t1, imm, dataSize=asz limm t4, 1 roli t4, t4, imm + mfence ldstl t1, seg, sib, disp sexti t0, t1, imm, flags=(CF,) or t1, t1, t4 stul t1, seg, sib, disp + mfence }; def macroop BTS_LOCKED_P_I { @@ -333,10 +351,12 @@ def macroop BTS_LOCKED_P_I { limm t1, imm, dataSize=asz limm t4, 1 roli t4, t4, imm + mfence ldstl t1, seg, riprel, disp sexti t0, t1, imm, flags=(CF,) or t1, t1, t4 stul t1, seg, riprel, disp + mfence }; def macroop BTS_R_R { @@ -377,10 +397,12 @@ def macroop BTS_LOCKED_M_R { lea t3, flatseg, [dsz, t3, base], dataSize=asz limm t4, 1 rol t4, t4, reg + mfence ldstl t1, seg, [scale, index, t3], disp sext t0, t1, reg, flags=(CF,) or t1, t1, t4 stul t1, seg, [scale, index, t3], disp + mfence }; def macroop BTS_LOCKED_P_R { @@ -390,9 +412,11 @@ def macroop BTS_LOCKED_P_R { lea t3, flatseg, [dsz, t3, base], dataSize=asz limm t4, 1 rol t4, t4, reg + mfence ldstl t1, seg, [1, t3, t7], disp sext t0, t1, reg, flags=(CF,) or t1, t1, t4 stul t1, seg, [1, t3, t7], disp + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py index 6504b5ab4..1518ce5e0 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py @@ -50,46 +50,58 @@ def macroop XCHG_R_R def macroop XCHG_R_M { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_R_P { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; def macroop XCHG_M_R { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; def macroop XCHG_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/logical.py b/src/arch/x86/isa/insts/general_purpose/logical.py index b8d442a02..49dea86e5 100644 --- a/src/arch/x86/isa/insts/general_purpose/logical.py +++ b/src/arch/x86/isa/insts/general_purpose/logical.py @@ -61,18 +61,22 @@ def macroop OR_P_I def macroop OR_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop OR_LOCKED_P_I { limm t2, imm rdip t7 + mfence ldstl t1, seg, riprel, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop OR_M_R @@ -92,17 +96,21 @@ def macroop OR_P_R def macroop OR_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop OR_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop OR_R_M @@ -155,18 +163,22 @@ def macroop XOR_P_I def macroop XOR_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop XOR_LOCKED_P_I { limm t2, imm rdip t7 + mfence ldstl t1, seg, riprel, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop XOR_M_R @@ -186,17 +198,21 @@ def macroop XOR_P_R def macroop XOR_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop XOR_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop XOR_R_M @@ -255,19 +271,23 @@ def macroop AND_P_I def macroop AND_LOCKED_M_I { + mfence ldstl t2, seg, sib, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) stul t2, seg, sib, disp + mfence }; def macroop AND_LOCKED_P_I { rdip t7 + mfence ldstl t2, seg, riprel, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) stul t2, seg, riprel, disp + mfence }; def macroop AND_M_R @@ -287,17 +307,21 @@ def macroop AND_P_R def macroop AND_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop AND_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop NOT_R @@ -326,17 +350,21 @@ def macroop NOT_P def macroop NOT_LOCKED_M { limm t1, -1 + mfence ldstl t2, seg, sib, disp xor t2, t2, t1 stul t2, seg, sib, disp + mfence }; def macroop NOT_LOCKED_P { limm t1, -1 rdip t7 + mfence ldstl t2, seg, riprel, disp xor t2, t2, t1 stul t2, seg, riprel, disp + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py b/src/arch/x86/isa/insts/general_purpose/semaphores.py index 072e28de6..17bee7fb7 100644 --- a/src/arch/x86/isa/insts/general_purpose/semaphores.py +++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py @@ -62,21 +62,25 @@ def macroop CMPXCHG_P_R { }; def macroop CMPXCHG_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) mov t1, t1, reg, flags=(CZF,) stul t1, seg, sib, disp + mfence mov rax, rax, t1, flags=(nCZF,) }; def macroop CMPXCHG_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) mov t1, t1, reg, flags=(CZF,) stul t1, seg, riprel, disp + mfence mov rax, rax, t1, flags=(nCZF,) }; @@ -96,17 +100,21 @@ def macroop XADD_P_R { }; def macroop XADD_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t2, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XADD_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t2, seg, riprel, disp + mfence mov reg, reg, t1 }; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 52420f175..5c242e2c9 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -1,4 +1,5 @@ // Copyright (c) 2007-2008 The Hewlett-Packard Development Company +// Copyright (c) 2011 Mark D. Hill and David A. Wood // All rights reserved. // // The license below extends only to copyright in the software and shall @@ -203,3 +204,55 @@ let {{ microopClasses["halt"] = Halt }}; + +def template MicroFenceOpDeclare {{ + class %(class_name)s : public X86ISA::X86MicroopBase + { + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + uint64_t setFlags); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroFenceOpConstructor {{ + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, uint64_t setFlags) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + setFlags, %(op_class)s) + { + %(constructor)s; + } +}}; + +let {{ + class MfenceOp(X86Microop): + def __init__(self): + self.className = "Mfence" + self.mnemonic = "mfence" + self.instFlags = "| (1ULL << StaticInst::IsMemBarrier)" + + def getAllocator(self, microFlags): + allocString = ''' + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s)) + ''' + allocator = allocString % { + "class_name" : self.className, + "mnemonic" : self.mnemonic, + "flags" : self.microFlagsText(microFlags) + self.instFlags} + return allocator + + microopClasses["mfence"] = MfenceOp +}}; + +let {{ + # Build up the all register version of this micro op + iop = InstObjParams("mfence", "Mfence", 'X86MicroopBase', + {"code" : ""}) + header_output += MicroFenceOpDeclare.subst(iop) + decoder_output += MicroFenceOpConstructor.subst(iop) + exec_output += BasicExecute.subst(iop) +}}; -- cgit v1.2.3