From 3e5f4876630169e92b3ad736d747bcba1b79c062 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 19 Apr 2009 04:25:01 -0700
Subject: Memory: Rename LOCKED for load locked store conditional to LLSC.

---
 src/arch/alpha/isa/decoder.isa | 8 ++++----
 src/arch/alpha/isa/pal.isa     | 2 +-
 src/arch/mips/isa/decoder.isa  | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'src/arch')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 0b2a31410..278ce31e8 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -45,8 +45,8 @@ decode OPCODE default Unknown::unknown() {
         0x0c: ldwu({{ Ra.uq = Mem.uw; }});
         0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
         0x23: ldt({{ Fa = Mem.df; }});
-        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
-        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
+        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
+        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
 #ifdef USE_COPY
         0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
                                       {{ fault = xc->copySrcTranslate(EA); }},
@@ -87,7 +87,7 @@ decode OPCODE default Unknown::unknown() {
                         if (tmp == 1) {
                             xc->setStCondFailures(0);
                         }
-                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
+                    }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
         0x2f: stq_c({{ Mem.uq = Ra; }},
                     {{
                         uint64_t tmp = write_result;
@@ -105,7 +105,7 @@ decode OPCODE default Unknown::unknown() {
                             // only.
                             xc->setStCondFailures(0);
                         }
-                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
+                    }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
     }
 
     format IntegerOperate {
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 3d3b81600..0931c1aec 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -178,7 +178,7 @@ output decoder {{
         if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
         if (HW_LDST_ALT)  memAccessFlags.set(Request::ALTMODE);
         if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE);
-        if (HW_LDST_LOCK) memAccessFlags.set(Request::LOCKED);
+        if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
     }
 
     std::string
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 68a63a458..a463093ec 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -2089,7 +2089,7 @@ decode OPCODE_HI default Unknown::unknown() {
 
     0x6: decode OPCODE_LO {
         format LoadMemory {
-            0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
+            0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC);
             0x1: lwc1({{ Ft.uw = Mem.uw; }});
             0x5: ldc1({{ Ft.ud = Mem.ud; }});
         }
@@ -2103,7 +2103,7 @@ decode OPCODE_HI default Unknown::unknown() {
         0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
                            {{ uint64_t tmp = write_result;
                               Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
-                           }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
+                           }}, mem_flags=LLSC, inst_flags = IsStoreConditional);
 
         format StoreMemory {
           0x1: swc1({{ Mem.uw = Ft.uw;}});
-- 
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