From 4cc31e1aefc337fe37c4b6373fe263e8b26e0b7d Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Fri, 9 Jun 2006 17:07:13 -0400
Subject: add fcntl64Func

use ThreadContext rename

src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/includes.isa:
    Use ThreadContext
src/sim/syscall_emul.cc:
    fcntl64 function using TC
src/sim/syscall_emul.hh:
    Add fcntl64func

--HG--
extra : convert_revision : b5e2348530473704388b1c5a2b59bf78360260a9
---
 src/arch/mips/isa/formats/branch.isa |  8 ++++----
 src/arch/mips/isa/formats/fp.isa     | 14 +++++++-------
 src/arch/mips/isa/includes.isa       |  2 +-
 3 files changed, 12 insertions(+), 12 deletions(-)

(limited to 'src/arch')

diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 6f8cebed0..e8843da03 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -88,7 +88,7 @@ output header {{
         {
         }
 
-        Addr branchTarget(ExecContext *xc) const;
+        Addr branchTarget(ThreadContext *tc) const;
 
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -103,10 +103,10 @@ output decoder {{
     }
 
     Addr
-    Jump::branchTarget(ExecContext *xc) const
+    Jump::branchTarget(ThreadContext *tc) const
     {
-        Addr NPC = xc->readPC() + 4;
-        uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+        Addr NPC = tc->readPC() + 4;
+        uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
         return (Rb & ~3) | (NPC & 1);
     }
 
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 6647f9361..1803c0e73 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -95,7 +95,7 @@ output exec {{
 
         template <class T>
         bool
-        fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *xc, const T dest_val,
+        fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
                     Trace::InstRecord *traceData)
         {
             uint64_t mips_nan = 0;
@@ -111,13 +111,13 @@ output exec {{
                 }
 
                 //Set value to QNAN
-                xc->setFloatRegBits(inst, 0, mips_nan, size);
+                cpu->setFloatRegBits(inst, 0, mips_nan, size);
 
                 //Read FCSR from FloatRegFile
-                uint32_t fcsr_bits = xc->cpuXC->readFloatRegBits(FCSR);
+                uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
 
                 //Write FCSR from FloatRegFile
-                xc->cpuXC->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
+                cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
 
                 if (traceData) { traceData->setData(mips_nan); }
                 return true;
@@ -127,15 +127,15 @@ output exec {{
         }
 
         void
-        fpResetCauseBits(%(CPU_exec_context)s *xc)
+        fpResetCauseBits(%(CPU_exec_context)s *cpu)
         {
             //Read FCSR from FloatRegFile
-            uint32_t fcsr = xc->cpuXC->readFloatRegBits(FCSR);
+            uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
 
             fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
 
             //Write FCSR from FloatRegFile
-            xc->cpuXC->setFloatRegBits(FCSR, fcsr);
+            cpu->tc->setFloatRegBits(FCSR, fcsr);
         }
 }};
 
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index fe21d65cb..126929e19 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -18,7 +18,7 @@ output decoder {{
 #include "arch/mips/isa_traits.hh"
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"  // for Jump::branchTarget()
+#include "cpu/thread_context.hh"
 #include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
-- 
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