From 5179d0ba2b573435796f9fd9cb6a25c82f5fc292 Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Tue, 7 Nov 2017 11:45:47 -0500 Subject: arch-riscv: Move static_inst into a directory This patch creates an "insts" directory in src/arch/riscv to store static portions of instruction definitions that aren't part of the code generated by the ISA description. It serves as a starting point for future patches to simplify the ISA description. Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa Reviewed-on: https://gem5-review.googlesource.com/6021 Reviewed-by: Gabe Black Maintainer: Alec Roelke --- src/arch/riscv/insts/SConscript | 4 ++ src/arch/riscv/insts/static_inst.cc | 19 +++++ src/arch/riscv/insts/static_inst.hh | 120 +++++++++++++++++++++++++++++++ src/arch/riscv/isa/includes.isa | 2 +- src/arch/riscv/static_inst.hh | 139 ------------------------------------ 5 files changed, 144 insertions(+), 140 deletions(-) create mode 100644 src/arch/riscv/insts/SConscript create mode 100644 src/arch/riscv/insts/static_inst.cc create mode 100644 src/arch/riscv/insts/static_inst.hh delete mode 100644 src/arch/riscv/static_inst.hh (limited to 'src/arch') diff --git a/src/arch/riscv/insts/SConscript b/src/arch/riscv/insts/SConscript new file mode 100644 index 000000000..95e6afd61 --- /dev/null +++ b/src/arch/riscv/insts/SConscript @@ -0,0 +1,4 @@ +Import('*') + +if env['TARGET_ISA'] == 'riscv': + Source('static_inst.cc') \ No newline at end of file diff --git a/src/arch/riscv/insts/static_inst.cc b/src/arch/riscv/insts/static_inst.cc new file mode 100644 index 000000000..8fc396d14 --- /dev/null +++ b/src/arch/riscv/insts/static_inst.cc @@ -0,0 +1,19 @@ +#include "arch/riscv/insts/static_inst.hh" + +#include "arch/riscv/types.hh" +#include "cpu/static_inst.hh" + +namespace RiscvISA +{ + +void +RiscvMicroInst::advancePC(PCState &pcState) const +{ + if (flags[IsLastMicroop]) { + pcState.uEnd(); + } else { + pcState.uAdvance(); + } +} + +} // namespace RiscvISA \ No newline at end of file diff --git a/src/arch/riscv/insts/static_inst.hh b/src/arch/riscv/insts/static_inst.hh new file mode 100644 index 000000000..d360d44d1 --- /dev/null +++ b/src/arch/riscv/insts/static_inst.hh @@ -0,0 +1,120 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2015 RISC-V Foundation +// Copyright (c) 2016 The University of Virginia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Maxwell Walter +// Alec Roelke + +#ifndef __ARCH_RISCV_STATIC_INST_HH__ +#define __ARCH_RISCV_STATIC_INST_HH__ + +#include + +#include "arch/riscv/types.hh" +#include "cpu/exec_context.hh" +#include "cpu/static_inst.hh" +#include "mem/packet.hh" + +namespace RiscvISA +{ + +/** + * Base class for all RISC-V static instructions. + */ +class RiscvStaticInst : public StaticInst +{ + protected: + using StaticInst::StaticInst; + + virtual std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; + + public: + void advancePC(PCState &pc) const { pc.advance(); } +}; + +/** + * Base class for all RISC-V Macroops + */ +class RiscvMacroInst : public RiscvStaticInst +{ + protected: + std::vector microops; + + // Constructor + RiscvMacroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + RiscvStaticInst(mnem, _machInst, __opClass) + { + flags[IsMacroop] = true; + } + + ~RiscvMacroInst() { microops.clear(); } + + StaticInstPtr fetchMicroop(MicroPC upc) const { return microops[upc]; } + + Fault + initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + completeAcc(PacketPtr pkt, ExecContext *xc, + Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + execute(ExecContext *xc, Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } +}; + +/** + * Base class for all RISC-V Microops + */ +class RiscvMicroInst : public RiscvStaticInst +{ + protected: + // Constructor + RiscvMicroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + RiscvStaticInst(mnem, _machInst, __opClass) + { + flags[IsMicroop] = true; + } + + void advancePC(PCState &pcState) const; +}; + +} + +#endif // __ARCH_RISCV_STATIC_INST_HH__ diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index c172d0300..48f2b1957 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -42,7 +42,7 @@ output header {{ #include #include -#include "arch/riscv/static_inst.hh" +#include "arch/riscv/insts/static_inst.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" #include "mem/request.hh" diff --git a/src/arch/riscv/static_inst.hh b/src/arch/riscv/static_inst.hh deleted file mode 100644 index bdcdee74a..000000000 --- a/src/arch/riscv/static_inst.hh +++ /dev/null @@ -1,139 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2015 RISC-V Foundation -// Copyright (c) 2016 The University of Virginia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Maxwell Walter -// Alec Roelke - -#ifndef __ARCH_RISCV_STATIC_INST_HH__ -#define __ARCH_RISCV_STATIC_INST_HH__ - -//////////////////////////////////////////////////////////////////// -// -// Base class for Riscv instructions, and some support functions -// - -namespace RiscvISA { - -/** - * Base class for all RISC-V static instructions. - */ -class RiscvStaticInst : public StaticInst -{ - protected: - // Constructor - RiscvStaticInst(const char *mnem, MachInst _machInst, - OpClass __opClass) : StaticInst(mnem, _machInst, __opClass) - {} - - virtual std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; - - public: - void - advancePC(RiscvISA::PCState &pc) const - { - pc.advance(); - } -}; - -/** - * Base class for all RISC-V Macroops - */ -class RiscvMacroInst : public RiscvStaticInst -{ - protected: - std::vector microops; - - // Constructor - RiscvMacroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - RiscvStaticInst(mnem, _machInst, __opClass) - { - flags[IsMacroop] = true; - } - - ~RiscvMacroInst() - { - microops.clear(); - } - - StaticInstPtr - fetchMicroop(MicroPC upc) const - { - return microops[upc]; - } - - Fault - initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - } - - Fault - completeAcc(PacketPtr pkt, ExecContext *xc, - Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - } - - Fault - execute(ExecContext *xc, Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - } -}; - -/** - * Base class for all RISC-V Microops - */ -class RiscvMicroInst : public RiscvStaticInst -{ - protected: - // Constructor - RiscvMicroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - RiscvStaticInst(mnem, _machInst, __opClass) - { - flags[IsMicroop] = true; - } - - void - advancePC(RiscvISA::PCState &pcState) const - { - if (flags[IsLastMicroop]) { - pcState.uEnd(); - } else { - pcState.uAdvance(); - } - } -}; - -} - -#endif // __ARCH_RISCV_STATIC_INST_HH__ -- cgit v1.2.3