From 57e951f6eae1de88988a9b13035c07985a0bcd73 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 4 Nov 2019 16:27:34 -0800 Subject: arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs. This conditional compilation was unnecessary and makes gem5 more brittle and harder to understand. Change-Id: I63abaf2668252c988cdd4626ff6a462eb6f54b04 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22544 Reviewed-by: Giacomo Travaglini Reviewed-by: Jason Lowe-Power Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/registers.hh | 2 -- src/arch/x86/registers.hh | 2 -- 2 files changed, 4 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index a97a4ce25..84f382b9c 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -102,8 +102,6 @@ const int INTRLVREG1 = INTRLVREG0 + 1; const int INTRLVREG2 = INTRLVREG0 + 2; const int INTRLVREG3 = INTRLVREG0 + 3; -#define ISA_HAS_CC_REGS - const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + NumVecPredRegs + NumMiscRegs; diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh index 0590abe49..479eda118 100644 --- a/src/arch/x86/registers.hh +++ b/src/arch/x86/registers.hh @@ -60,8 +60,6 @@ const int NumIntArchRegs = NUM_INTREGS; const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs; const int NumCCRegs = NUM_CCREGS; -#define ISA_HAS_CC_REGS - // Each 128 bit xmm register is broken into two effective 64 bit registers. // Add 8 for the indices that are mapped over the fp stack const int NumFloatRegs = -- cgit v1.2.3