From 5a9a743cfc4517f93e5c94533efa767b92272c59 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 13 Feb 2012 06:43:09 -0500 Subject: MEM: Introduce the master/slave port roles in the Python classes This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves. --- src/arch/arm/ArmTLB.py | 2 +- src/arch/x86/X86LocalApic.py | 15 ++++++++++++++- src/arch/x86/X86TLB.py | 2 +- src/arch/x86/interrupts.hh | 22 +++++++++++++++++++++- 4 files changed, 37 insertions(+), 4 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index fc6f51d84..8599fa75f 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -45,7 +45,7 @@ from MemObject import MemObject class ArmTableWalker(MemObject): type = 'ArmTableWalker' cxx_class = 'ArmISA::TableWalker' - port = Port("Port for TableWalker to do walk the translation with") + port = MasterPort("Port for TableWalker to do walk the translation with") sys = Param.System(Parent.any, "system object parameter") min_backoff = Param.Tick(0, "Minimum backoff delay after failed send") max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send") diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py index 2f53c4e24..283d94ba7 100644 --- a/src/arch/x86/X86LocalApic.py +++ b/src/arch/x86/X86LocalApic.py @@ -1,3 +1,15 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2008 The Regents of The University of Michigan # All rights reserved. # @@ -35,6 +47,7 @@ class X86LocalApic(BasicPioDevice): type = 'X86LocalApic' cxx_class = 'X86ISA::Interrupts' pio_latency = Param.Latency('1ns', 'Programmed IO latency in simticks') - int_port = Port("Port for sending and receiving interrupt messages") + int_master = MasterPort("Port for sending interrupt messages") + int_slave = SlavePort("Port for receiving interrupt messages") int_latency = Param.Latency('1ns', \ "Latency for an interrupt to propagate through this device.") diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 7f2fcd358..334d2a0cf 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -44,7 +44,7 @@ from MemObject import MemObject class X86PagetableWalker(MemObject): type = 'X86PagetableWalker' cxx_class = 'X86ISA::Walker' - port = Port("Port for the hardware table walker") + port = MasterPort("Port for the hardware table walker") system = Param.System(Parent.any, "system object") class X86TLB(BaseTLB): diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index 8567b30f0..13ad2069b 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2007 The Hewlett-Packard Development Company * All rights reserved. * @@ -35,6 +47,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black + * Andreas Hansson */ #ifndef __ARCH_X86_INTERRUPTS_HH__ @@ -225,8 +238,15 @@ class Interrupts : public BasicPioDevice, IntDev Port *getPort(const std::string &if_name, int idx = -1) { - if (if_name == "int_port") + // a bit of an odd one since there is now two ports in the + // Python class we also need two ports even if they are + // identical + if (if_name == "int_master") { return intPort; + } else if (if_name == "int_slave") { + // memory leak...but will be removed in the next patch + return new IntPort(name() + ".int_slave", this, this, latency); + } return BasicPioDevice::getPort(if_name, idx); } -- cgit v1.2.3