From 67d58e81825d7dff17def2cfeedf5d958141be55 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Thu, 20 Sep 2018 14:13:11 +0100
Subject: arch-arm: Add Crypto in SE mode
This patch is also enabling AArch32 crypto instructions by setting the
ID_ISAR5 register accordingly.
Change-Id: Id412585b39b78570a65bd3047199c84e9db76cda
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15155
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
src/arch/arm/isa.cc | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
(limited to 'src/arch')
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a4ebfc1db..319cc9c09 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -89,7 +89,7 @@ ISA::ISA(Params *p)
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
haveSecurity = haveLPAE = haveVirtualization = false;
- haveCrypto = false;
+ haveCrypto = true;
haveLargeAsid64 = false;
physAddrRange = 32; // dummy value
}
@@ -315,6 +315,10 @@ ISA::initID32(const ArmISAParams *p)
miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
+ miscRegs[MISCREG_ID_ISAR5] = insertBits(
+ miscRegs[MISCREG_ID_ISAR5], 19, 4,
+ haveCrypto ? 0x1112 : 0x0);
}
void
--
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