From 68300cfb8c6099cc84cb3e544950c0e6a154ff07 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:21:08 -0800 Subject: X86: Make rdcr use merge and the mov to control register instructions use the right operand size. --- src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 2 ++ src/arch/x86/isa/microops/regop.isa | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py index abe44ae59..dded94968 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py @@ -192,10 +192,12 @@ def macroop MOVZX_W_R_P { }; def macroop MOV_C_R { + .adjust_env maxOsz wrcr reg, regm }; def macroop MOV_R_C { + .adjust_env maxOsz rdcr reg, regm }; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 1349a64c2..7c2feb398 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -967,7 +967,7 @@ let {{ if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { fault = new InvalidOpcode(); } else { - DestReg = ControlSrc1; + DestReg = merge(DestReg, ControlSrc1, dataSize); } ''' -- cgit v1.2.3