From 689221c651035ebb8be411893a9cc73f17bba9fb Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 20 Feb 2018 13:33:34 +0000 Subject: arch-arm: Fix PCAlignmentFault routing to Hypervisor This patch enables PCAlignmentFault routing to Hypervisor in case HCR_EL2.TGE == 1, as is happening for other arm exceptions. Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/8841 Maintainer: Andreas Sandberg --- src/arch/arm/faults.cc | 14 ++++++++++++++ src/arch/arm/faults.hh | 1 + 2 files changed, 15 insertions(+) (limited to 'src/arch') diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index c36848ecf..1d6d01592 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1432,6 +1432,20 @@ PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) tc->setMiscReg(getFaultAddrReg64(), faultPC); } +bool +PCAlignmentFault::routeToHyp(ThreadContext *tc) const +{ + bool toHyp = false; + + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); + CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); + + // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector + toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); + return toHyp; +} + SPAlignmentFault::SPAlignmentFault() {} diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index d99116fb9..537405cf2 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -535,6 +535,7 @@ class PCAlignmentFault : public ArmFaultVals {} void invoke(ThreadContext *tc, const StaticInstPtr &inst = StaticInst::nullStaticInstPtr) override; + bool routeToHyp(ThreadContext *tc) const override; }; /// Stack pointer alignment fault (AArch64 only) -- cgit v1.2.3