From 6eb434c8a227cdc30b459b2b96cb4354e3312554 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 21 Aug 2015 07:03:25 -0400 Subject: arm, mem: Remove unused CLEAR_LL request flag Cleaning up dead code. The CLREX stores zero directly to MISCREG_LOCKFLAG and so the request flag is no longer needed. The corresponding functionality in the cache tags is also removed. --- src/arch/arm/tlb.cc | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 11075f02c..aee6a251a 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -977,16 +977,6 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2, scr, sctlr, flags, tranType); - // If this is a clrex instruction, provide a PA of 0 with no fault - // This will force the monitor to set the tracked address to 0 - // a bit of a hack but this effectively clrears this processors monitor - if (flags & Request::CLEAR_LL){ - // @todo: check implications of security extensions - req->setPaddr(0); - req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); - req->setFlags(Request::CLEAR_LL); - return NoFault; - } if ((req->isInstFetch() && (!sctlr.i)) || ((!req->isInstFetch()) && (!sctlr.c))){ req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); -- cgit v1.2.3