From 5639fb2c431fffa11392f34f90619fac806aa277 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Mon, 12 Jun 2006 18:58:29 -0400
Subject: Fix memory leak.

src/arch/alpha/ev5.cc:
    Fix memory leak.  The faults are refcounted, but that only works if you're actually assigning them to a RefCountingPtr.

--HG--
extra : convert_revision : 9a57963eb5d5d86c16023bfedb0fb5ccdbe7efaa
---
 src/arch/alpha/ev5.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'src/arch')

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index c419762b7..247c5f56e 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -59,8 +59,12 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
     tc->setIntReg(16, cpuId);
     tc->setIntReg(0, cpuId);
 
-    tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
+    AlphaFault *reset = new ResetFault;
+
+    tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
     tc->setNextPC(tc->readPC() + sizeof(MachInst));
+
+    delete reset;
 }
 
 ////////////////////////////////////////////////////////////////////////
-- 
cgit v1.2.3


From fbf3a82c5c358d75acd9a97ad1dcef9796b83c96 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Mon, 12 Jun 2006 18:59:24 -0400
Subject: Fix compile error.

--HG--
extra : convert_revision : 334f5033f5a3a303bfaec3a3acfbd36f205efe86
---
 src/arch/mips/isa/formats/branch.isa | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/arch')

diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 8cfa37a20..ea5af22c0 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -111,7 +111,7 @@ output header {{
         {
         }
 
-        Addr branchTarget(ExecContext *xc) const;
+        Addr branchTarget(ThreadContext *tc) const;
 
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -132,10 +132,10 @@ output decoder {{
     }
 
     Addr
-    Jump::branchTarget(ExecContext *xc) const
+    Jump::branchTarget(ThreadContext *tc) const
     {
-        Addr NPC = xc->readPC() + 4;
-        uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+        Addr NPC = tc->readPC() + 4;
+        uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
         return (Rb & ~3) | (NPC & 1);
     }
 
-- 
cgit v1.2.3


From b5cf61efad0acab998b17623ebb00f67cb1f6d50 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Mon, 12 Jun 2006 19:11:38 -0400
Subject: Fixes for checker.  The RC/RS instructions check the interrupt flag,
 which isn't verifiable by the checker.

src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
    Fixes for checker.

--HG--
extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e
---
 src/arch/alpha/isa/decoder.isa | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/arch')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index fab2ca2e1..dd29e47e4 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -659,11 +659,11 @@ decode OPCODE default Unknown::unknown() {
             0xe000: rc({{
                 Ra = xc->readIntrFlag();
                 xc->setIntrFlag(0);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
             0xf000: rs({{
                 Ra = xc->readIntrFlag();
                 xc->setIntrFlag(1);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
         }
 #else
         format FailUnimpl {
-- 
cgit v1.2.3