From 7aa423acad07f05ee547117406a72a5c1b4f6015 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 15 Oct 2013 14:22:42 -0400 Subject: cpu: clean up architectural register classification Move from a poorly documented scheme where the mapping of unified architectural register indices to register classes is hardcoded all over to one where there's an enum for the register classes and a function that encapsulates the mapping. --- src/arch/arm/insts/misc.cc | 12 ++++---- src/arch/arm/insts/static_inst.cc | 23 ++++++++++------ src/arch/power/insts/static_inst.cc | 30 ++++++++++++-------- src/arch/x86/insts/static_inst.cc | 55 ++++++++++++++++++++++--------------- 4 files changed, 74 insertions(+), 46 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 7d383a87a..c40b6711f 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2010 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -38,6 +39,7 @@ */ #include "arch/arm/insts/misc.hh" +#include "cpu/reg_class.hh" std::string MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const @@ -48,17 +50,17 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const ss << ", "; bool foundPsr = false; for (unsigned i = 0; i < numSrcRegs(); i++) { - int idx = srcRegIdx(i); - if (idx < Ctrl_Base_DepTag) { + RegIndex idx = srcRegIdx(i); + RegIndex rel_idx; + if (regIdxToClass(idx, &rel_idx) != MiscRegClass) { continue; } - idx -= Ctrl_Base_DepTag; - if (idx == MISCREG_CPSR) { + if (rel_idx == MISCREG_CPSR) { ss << "cpsr"; foundPsr = true; break; } - if (idx == MISCREG_SPSR) { + if (rel_idx == MISCREG_SPSR) { ss << "spsr"; foundPsr = true; break; diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 8306c620f..3ab7dfb0e 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2010 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -45,6 +46,7 @@ #include "base/loader/symtab.hh" #include "base/condcodes.hh" #include "base/cprintf.hh" +#include "cpu/reg_class.hh" namespace ArmISA { @@ -208,8 +210,11 @@ ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt, void ArmStaticInst::printReg(std::ostream &os, int reg) const { - if (reg < FP_Base_DepTag) { - switch (reg) { + RegIndex rel_reg; + + switch (regIdxToClass(reg, &rel_reg)) { + case IntRegClass: + switch (rel_reg) { case PCReg: ccprintf(os, "pc"); break; @@ -226,12 +231,14 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const ccprintf(os, "r%d", reg); break; } - } else if (reg < Ctrl_Base_DepTag) { - ccprintf(os, "f%d", reg - FP_Base_DepTag); - } else { - reg -= Ctrl_Base_DepTag; - assert(reg < NUM_MISCREGS); - ccprintf(os, "%s", ArmISA::miscRegName[reg]); + break; + case FloatRegClass: + ccprintf(os, "f%d", rel_reg); + break; + case MiscRegClass: + assert(rel_reg < NUM_MISCREGS); + ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]); + break; } } diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc index 1982744bf..09b662453 100644 --- a/src/arch/power/insts/static_inst.cc +++ b/src/arch/power/insts/static_inst.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,23 +30,30 @@ */ #include "arch/power/insts/static_inst.hh" +#include "cpu/reg_class.hh" using namespace PowerISA; void PowerStaticInst::printReg(std::ostream &os, int reg) const { - if (reg < FP_Base_DepTag) { - ccprintf(os, "r%d", reg); - } else if (reg < Ctrl_Base_DepTag) { - ccprintf(os, "f%d", reg - FP_Base_DepTag); - } else { - switch (reg - Ctrl_Base_DepTag) { - case 0: ccprintf(os, "cr"); break; - case 1: ccprintf(os, "xer"); break; - case 2: ccprintf(os, "lr"); break; - case 3: ccprintf(os, "ctr"); break; - default: ccprintf(os, "unknown_reg"); + RegIndex rel_reg; + + switch (regIdxToClass(reg, &rel_reg)) { + case IntRegClass: + ccprintf(os, "r%d", rel_reg); + break; + case FloatRegClass: + ccprintf(os, "f%d", rel_reg); + break; + case MiscRegClass: + switch (rel_reg) { + case 0: ccprintf(os, "cr"); break; + case 1: ccprintf(os, "xer"); break; + case 2: ccprintf(os, "lr"); break; + case 3: ccprintf(os, "ctr"); break; + default: ccprintf(os, "unknown_reg"); + break; } } } diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc index 29957e121..046a11fb6 100644 --- a/src/arch/x86/insts/static_inst.cc +++ b/src/arch/x86/insts/static_inst.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2007 The Hewlett-Packard Development Company + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -39,6 +40,7 @@ #include "arch/x86/insts/static_inst.hh" #include "arch/x86/regs/segment.hh" +#include "cpu/reg_class.hh" namespace X86ISA { @@ -129,17 +131,20 @@ namespace X86ISA static const char * microFormats[9] = {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"}; - if (reg < FP_Base_DepTag) { + RegIndex rel_reg; + + switch (regIdxToClass(reg, &rel_reg)) { + case IntRegClass: { const char * suffix = ""; - bool fold = reg & IntFoldBit; - reg &= ~IntFoldBit; + bool fold = rel_reg & IntFoldBit; + rel_reg &= ~IntFoldBit; if(fold) suffix = "h"; - else if(reg < 8 && size == 1) + else if(rel_reg < 8 && size == 1) suffix = "l"; - switch (reg) { + switch (rel_reg) { case INTREG_RAX: ccprintf(os, abcdFormats[size], "a"); break; @@ -189,33 +194,39 @@ namespace X86ISA ccprintf(os, longFormats[size], "15"); break; default: - ccprintf(os, microFormats[size], reg - NUM_INTREGS); + ccprintf(os, microFormats[size], rel_reg - NUM_INTREGS); } ccprintf(os, suffix); - } else if (reg < Ctrl_Base_DepTag) { - int fpindex = reg - FP_Base_DepTag; - if(fpindex < NumMMXRegs) { - ccprintf(os, "%%mmx%d", reg - FP_Base_DepTag); + break; + } + + case FloatRegClass: { + if (rel_reg < NumMMXRegs) { + ccprintf(os, "%%mmx%d", rel_reg); return; } - fpindex -= NumMMXRegs; - if(fpindex < NumXMMRegs * 2) { - ccprintf(os, "%%xmm%d_%s", fpindex / 2, - (fpindex % 2) ? "high": "low"); + rel_reg -= NumMMXRegs; + if (rel_reg < NumXMMRegs * 2) { + ccprintf(os, "%%xmm%d_%s", rel_reg / 2, + (rel_reg % 2) ? "high": "low"); return; } - fpindex -= NumXMMRegs * 2; - if(fpindex < NumMicroFpRegs) { - ccprintf(os, "%%ufp%d", fpindex); + rel_reg -= NumXMMRegs * 2; + if (rel_reg < NumMicroFpRegs) { + ccprintf(os, "%%ufp%d", rel_reg); return; } - fpindex -= NumMicroFpRegs; - ccprintf(os, "%%st(%d)", fpindex); - } else { - switch (reg - Ctrl_Base_DepTag) { + rel_reg -= NumMicroFpRegs; + ccprintf(os, "%%st(%d)", rel_reg); + break; + } + + case MiscRegClass: + switch (rel_reg) { default: - ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag); + ccprintf(os, "%%ctrl%d", rel_reg); } + break; } } -- cgit v1.2.3