From 936b584ce35c079db98ab17c6ac9c6943ce7220e Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 9 May 2018 15:59:38 +0100 Subject: arch-arm: Remove unusued MISCREG_A64_UNIMPL In case the decoder fails to find a suitable MiscReg during a MSR/MRS in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra MISCREG_A64_UNIMPL register. Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10503 Maintainer: Andreas Sandberg --- src/arch/arm/miscregs.cc | 3 --- src/arch/arm/miscregs.hh | 2 -- 2 files changed, 5 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 08e37bb70..31b3580be 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4007,9 +4007,6 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_CP15_UNIMPL) .unimplemented() .warnNotFail(); - InitReg(MISCREG_A64_UNIMPL) - .unimplemented() - .warnNotFail(); InitReg(MISCREG_UNKNOWN); // Register mappings for some unimplemented registers: diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index b43b04f72..b00e5ff66 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -689,7 +689,6 @@ namespace ArmISA MISCREG_RAZ, MISCREG_CP14_UNIMPL, MISCREG_CP15_UNIMPL, - MISCREG_A64_UNIMPL, MISCREG_UNKNOWN, // Implementation defined register: this represent @@ -1386,7 +1385,6 @@ namespace ArmISA "raz", "cp14_unimpl", "cp15_unimpl", - "a64_unimpl", "unknown", "impl_defined" }; -- cgit v1.2.3