From b5cf61efad0acab998b17623ebb00f67cb1f6d50 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Mon, 12 Jun 2006 19:11:38 -0400
Subject: Fixes for checker.  The RC/RS instructions check the interrupt flag,
 which isn't verifiable by the checker.

src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
    Fixes for checker.

--HG--
extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e
---
 src/arch/alpha/isa/decoder.isa | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/arch')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index fab2ca2e1..dd29e47e4 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -659,11 +659,11 @@ decode OPCODE default Unknown::unknown() {
             0xe000: rc({{
                 Ra = xc->readIntrFlag();
                 xc->setIntrFlag(0);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
             0xf000: rs({{
                 Ra = xc->readIntrFlag();
                 xc->setIntrFlag(1);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
         }
 #else
         format FailUnimpl {
-- 
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