From 4862879a9420c52d48532d957b616c458b643a1e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 02:08:44 -0500 Subject: Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names. --HG-- extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4 --- src/arch/alpha/tlb.cc | 926 +++++++++++++++++++++++++------------------------- src/arch/alpha/tlb.hh | 158 ++++----- 2 files changed, 546 insertions(+), 538 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index bab44c434..ae302e686 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -46,589 +46,591 @@ using namespace std; using namespace EV5; -/////////////////////////////////////////////////////////////////////// -// -// Alpha TLB -// +namespace AlphaISA +{ + /////////////////////////////////////////////////////////////////////// + // + // Alpha TLB + // #ifdef DEBUG -bool uncacheBit39 = false; -bool uncacheBit40 = false; + bool uncacheBit39 = false; + bool uncacheBit40 = false; #endif #define MODE2MASK(X) (1 << (X)) -AlphaTLB::AlphaTLB(const string &name, int s) - : SimObject(name), size(s), nlu(0) -{ - table = new AlphaISA::PTE[size]; - memset(table, 0, sizeof(AlphaISA::PTE[size])); -} + TLB::TLB(const string &name, int s) + : SimObject(name), size(s), nlu(0) + { + table = new PTE[size]; + memset(table, 0, sizeof(PTE[size])); + } -AlphaTLB::~AlphaTLB() -{ - if (table) - delete [] table; -} + TLB::~TLB() + { + if (table) + delete [] table; + } -// look up an entry in the TLB -AlphaISA::PTE * -AlphaTLB::lookup(Addr vpn, uint8_t asn) const -{ - // assume not found... - AlphaISA::PTE *retval = NULL; + // look up an entry in the TLB + PTE * + TLB::lookup(Addr vpn, uint8_t asn) const + { + // assume not found... + PTE *retval = NULL; + + PageTable::const_iterator i = lookupTable.find(vpn); + if (i != lookupTable.end()) { + while (i->first == vpn) { + int index = i->second; + PTE *pte = &table[index]; + assert(pte->valid); + if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { + retval = pte; + break; + } - PageTable::const_iterator i = lookupTable.find(vpn); - if (i != lookupTable.end()) { - while (i->first == vpn) { - int index = i->second; - AlphaISA::PTE *pte = &table[index]; - assert(pte->valid); - if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { - retval = pte; - break; + ++i; } - - ++i; } - } - DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, - retval ? "hit" : "miss", retval ? retval->ppn : 0); - return retval; -} + DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, + retval ? "hit" : "miss", retval ? retval->ppn : 0); + return retval; + } -Fault -AlphaTLB::checkCacheability(RequestPtr &req) -{ - // in Alpha, cacheability is controlled by upper-level bits of the - // physical address + Fault + TLB::checkCacheability(RequestPtr &req) + { + // in Alpha, cacheability is controlled by upper-level bits of the + // physical address - /* - * We support having the uncacheable bit in either bit 39 or bit 40. - * The Turbolaser platform (and EV5) support having the bit in 39, but - * Tsunami (which Linux assumes uses an EV6) generates accesses with - * the bit in 40. So we must check for both, but we have debug flags - * to catch a weird case where both are used, which shouldn't happen. - */ + /* + * We support having the uncacheable bit in either bit 39 or bit 40. + * The Turbolaser platform (and EV5) support having the bit in 39, but + * Tsunami (which Linux assumes uses an EV6) generates accesses with + * the bit in 40. So we must check for both, but we have debug flags + * to catch a weird case where both are used, which shouldn't happen. + */ #if ALPHA_TLASER - if (req->getPaddr() & PAddrUncachedBit39) { + if (req->getPaddr() & PAddrUncachedBit39) { #else - if (req->getPaddr() & PAddrUncachedBit43) { + if (req->getPaddr() & PAddrUncachedBit43) { #endif - // IPR memory space not implemented - if (PAddrIprSpace(req->getPaddr())) { - return new UnimpFault("IPR memory space not implemented!"); - } else { - // mark request as uncacheable - req->setFlags(req->getFlags() | UNCACHEABLE); + // IPR memory space not implemented + if (PAddrIprSpace(req->getPaddr())) { + return new UnimpFault("IPR memory space not implemented!"); + } else { + // mark request as uncacheable + req->setFlags(req->getFlags() | UNCACHEABLE); #if !ALPHA_TLASER - // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) - req->setPaddr(req->getPaddr() & PAddrUncachedMask); + // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) + req->setPaddr(req->getPaddr() & PAddrUncachedMask); #endif + } } + return NoFault; } - return NoFault; -} -// insert a new TLB entry -void -AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte) -{ - AlphaISA::VAddr vaddr = addr; - if (table[nlu].valid) { - Addr oldvpn = table[nlu].tag; - PageTable::iterator i = lookupTable.find(oldvpn); + // insert a new TLB entry + void + TLB::insert(Addr addr, PTE &pte) + { + VAddr vaddr = addr; + if (table[nlu].valid) { + Addr oldvpn = table[nlu].tag; + PageTable::iterator i = lookupTable.find(oldvpn); - if (i == lookupTable.end()) - panic("TLB entry not found in lookupTable"); - - int index; - while ((index = i->second) != nlu) { - if (table[index].tag != oldvpn) + if (i == lookupTable.end()) panic("TLB entry not found in lookupTable"); - ++i; + int index; + while ((index = i->second) != nlu) { + if (table[index].tag != oldvpn) + panic("TLB entry not found in lookupTable"); + + ++i; + } + + DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); + + lookupTable.erase(i); } - DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); + DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); - lookupTable.erase(i); - } + table[nlu] = pte; + table[nlu].tag = vaddr.vpn(); + table[nlu].valid = true; - DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); + lookupTable.insert(make_pair(vaddr.vpn(), nlu)); + nextnlu(); + } - table[nlu] = pte; - table[nlu].tag = vaddr.vpn(); - table[nlu].valid = true; + void + TLB::flushAll() + { + DPRINTF(TLB, "flushAll\n"); + memset(table, 0, sizeof(PTE[size])); + lookupTable.clear(); + nlu = 0; + } - lookupTable.insert(make_pair(vaddr.vpn(), nlu)); - nextnlu(); -} + void + TLB::flushProcesses() + { + PageTable::iterator i = lookupTable.begin(); + PageTable::iterator end = lookupTable.end(); + while (i != end) { + int index = i->second; + PTE *pte = &table[index]; + assert(pte->valid); -void -AlphaTLB::flushAll() -{ - DPRINTF(TLB, "flushAll\n"); - memset(table, 0, sizeof(AlphaISA::PTE[size])); - lookupTable.clear(); - nlu = 0; -} + // we can't increment i after we erase it, so save a copy and + // increment it to get the next entry now + PageTable::iterator cur = i; + ++i; -void -AlphaTLB::flushProcesses() -{ - PageTable::iterator i = lookupTable.begin(); - PageTable::iterator end = lookupTable.end(); - while (i != end) { - int index = i->second; - AlphaISA::PTE *pte = &table[index]; - assert(pte->valid); - - // we can't increment i after we erase it, so save a copy and - // increment it to get the next entry now - PageTable::iterator cur = i; - ++i; - - if (!pte->asma) { - DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); - pte->valid = false; - lookupTable.erase(cur); + if (!pte->asma) { + DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); + pte->valid = false; + lookupTable.erase(cur); + } } } -} -void -AlphaTLB::flushAddr(Addr addr, uint8_t asn) -{ - AlphaISA::VAddr vaddr = addr; + void + TLB::flushAddr(Addr addr, uint8_t asn) + { + VAddr vaddr = addr; - PageTable::iterator i = lookupTable.find(vaddr.vpn()); - if (i == lookupTable.end()) - return; + PageTable::iterator i = lookupTable.find(vaddr.vpn()); + if (i == lookupTable.end()) + return; - while (i->first == vaddr.vpn()) { - int index = i->second; - AlphaISA::PTE *pte = &table[index]; - assert(pte->valid); + while (i->first == vaddr.vpn()) { + int index = i->second; + PTE *pte = &table[index]; + assert(pte->valid); - if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { - DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), - pte->ppn); + if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { + DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), + pte->ppn); - // invalidate this entry - pte->valid = false; + // invalidate this entry + pte->valid = false; - lookupTable.erase(i); - } + lookupTable.erase(i); + } - ++i; + ++i; + } } -} -void -AlphaTLB::serialize(ostream &os) -{ - SERIALIZE_SCALAR(size); - SERIALIZE_SCALAR(nlu); + void + TLB::serialize(ostream &os) + { + SERIALIZE_SCALAR(size); + SERIALIZE_SCALAR(nlu); - for (int i = 0; i < size; i++) { - nameOut(os, csprintf("%s.PTE%d", name(), i)); - table[i].serialize(os); + for (int i = 0; i < size; i++) { + nameOut(os, csprintf("%s.PTE%d", name(), i)); + table[i].serialize(os); + } } -} -void -AlphaTLB::unserialize(Checkpoint *cp, const string §ion) -{ - UNSERIALIZE_SCALAR(size); - UNSERIALIZE_SCALAR(nlu); + void + TLB::unserialize(Checkpoint *cp, const string §ion) + { + UNSERIALIZE_SCALAR(size); + UNSERIALIZE_SCALAR(nlu); - for (int i = 0; i < size; i++) { - table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); - if (table[i].valid) { - lookupTable.insert(make_pair(table[i].tag, i)); + for (int i = 0; i < size; i++) { + table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); + if (table[i].valid) { + lookupTable.insert(make_pair(table[i].tag, i)); + } } } -} - -/////////////////////////////////////////////////////////////////////// -// -// Alpha ITB -// -AlphaITB::AlphaITB(const std::string &name, int size) - : AlphaTLB(name, size) -{} - -void -AlphaITB::regStats() -{ - hits - .name(name() + ".hits") - .desc("ITB hits"); - misses - .name(name() + ".misses") - .desc("ITB misses"); - acv - .name(name() + ".acv") - .desc("ITB acv"); - accesses - .name(name() + ".accesses") - .desc("ITB accesses"); - - accesses = hits + misses; -} - - -Fault -AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const -{ - if (AlphaISA::PcPAL(req->getVaddr())) { - // strip off PAL PC marker (lsb is 1) - req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); - hits++; - return NoFault; + /////////////////////////////////////////////////////////////////////// + // + // Alpha ITB + // + ITB::ITB(const std::string &name, int size) + : TLB(name, size) + {} + + + void + ITB::regStats() + { + hits + .name(name() + ".hits") + .desc("ITB hits"); + misses + .name(name() + ".misses") + .desc("ITB misses"); + acv + .name(name() + ".acv") + .desc("ITB acv"); + accesses + .name(name() + ".accesses") + .desc("ITB accesses"); + + accesses = hits + misses; } - if (req->getFlags() & PHYSICAL) { - req->setPaddr(req->getVaddr()); - } else { - // verify that this is a good virtual address - if (!validVirtualAddress(req->getVaddr())) { - acv++; - return new ItbAcvFault(req->getVaddr()); + + Fault + ITB::translate(RequestPtr &req, ThreadContext *tc) const + { + if (PcPAL(req->getVaddr())) { + // strip off PAL PC marker (lsb is 1) + req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); + hits++; + return NoFault; } + if (req->getFlags() & PHYSICAL) { + req->setPaddr(req->getVaddr()); + } else { + // verify that this is a good virtual address + if (!validVirtualAddress(req->getVaddr())) { + acv++; + return new ItbAcvFault(req->getVaddr()); + } + - // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 - // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 + // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 + // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #if ALPHA_TLASER - if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->getVaddr()) == 2) { + if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && + VAddrSpaceEV5(req->getVaddr()) == 2) { #else - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { #endif - // only valid in kernel mode - if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) != - AlphaISA::mode_kernel) { - acv++; - return new ItbAcvFault(req->getVaddr()); - } + // only valid in kernel mode + if (ICM_CM(tc->readMiscReg(IPR_ICM)) != + mode_kernel) { + acv++; + return new ItbAcvFault(req->getVaddr()); + } - req->setPaddr(req->getVaddr() & PAddrImplMask); + req->setPaddr(req->getVaddr() & PAddrImplMask); #if !ALPHA_TLASER - // sign extend the physical address properly - if (req->getPaddr() & PAddrUncachedBit40) - req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); - else - req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); + // sign extend the physical address properly + if (req->getPaddr() & PAddrUncachedBit40) + req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); + else + req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); #endif - } else { - // not a physical address: need to look up pte - int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); - AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), - asn); - - if (!pte) { - misses++; - return new ItbPageFault(req->getVaddr()); - } + } else { + // not a physical address: need to look up pte + int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN)); + PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), + asn); + + if (!pte) { + misses++; + return new ItbPageFault(req->getVaddr()); + } - req->setPaddr((pte->ppn << AlphaISA::PageShift) + - (AlphaISA::VAddr(req->getVaddr()).offset() - & ~3)); + req->setPaddr((pte->ppn << PageShift) + + (VAddr(req->getVaddr()).offset() + & ~3)); - // check permissions for this access - if (!(pte->xre & - (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) { - // instruction access fault - acv++; - return new ItbAcvFault(req->getVaddr()); - } + // check permissions for this access + if (!(pte->xre & + (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) { + // instruction access fault + acv++; + return new ItbAcvFault(req->getVaddr()); + } - hits++; + hits++; + } } - } - - // check that the physical address is ok (catch bad physical addresses) - if (req->getPaddr() & ~PAddrImplMask) - return genMachineCheckFault(); - return checkCacheability(req); - -} + // check that the physical address is ok (catch bad physical addresses) + if (req->getPaddr() & ~PAddrImplMask) + return genMachineCheckFault(); -/////////////////////////////////////////////////////////////////////// -// -// Alpha DTB -// -AlphaDTB::AlphaDTB(const std::string &name, int size) - : AlphaTLB(name, size) -{} + return checkCacheability(req); -void -AlphaDTB::regStats() -{ - read_hits - .name(name() + ".read_hits") - .desc("DTB read hits") - ; - - read_misses - .name(name() + ".read_misses") - .desc("DTB read misses") - ; - - read_acv - .name(name() + ".read_acv") - .desc("DTB read access violations") - ; - - read_accesses - .name(name() + ".read_accesses") - .desc("DTB read accesses") - ; - - write_hits - .name(name() + ".write_hits") - .desc("DTB write hits") - ; - - write_misses - .name(name() + ".write_misses") - .desc("DTB write misses") - ; - - write_acv - .name(name() + ".write_acv") - .desc("DTB write access violations") - ; - - write_accesses - .name(name() + ".write_accesses") - .desc("DTB write accesses") - ; - - hits - .name(name() + ".hits") - .desc("DTB hits") - ; - - misses - .name(name() + ".misses") - .desc("DTB misses") - ; - - acv - .name(name() + ".acv") - .desc("DTB access violations") - ; - - accesses - .name(name() + ".accesses") - .desc("DTB accesses") - ; - - hits = read_hits + write_hits; - misses = read_misses + write_misses; - acv = read_acv + write_acv; - accesses = read_accesses + write_accesses; -} + } -Fault -AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const -{ - Addr pc = tc->readPC(); + /////////////////////////////////////////////////////////////////////// + // + // Alpha DTB + // + DTB::DTB(const std::string &name, int size) + : TLB(name, size) + {} + + void + DTB::regStats() + { + read_hits + .name(name() + ".read_hits") + .desc("DTB read hits") + ; + + read_misses + .name(name() + ".read_misses") + .desc("DTB read misses") + ; + + read_acv + .name(name() + ".read_acv") + .desc("DTB read access violations") + ; + + read_accesses + .name(name() + ".read_accesses") + .desc("DTB read accesses") + ; + + write_hits + .name(name() + ".write_hits") + .desc("DTB write hits") + ; + + write_misses + .name(name() + ".write_misses") + .desc("DTB write misses") + ; + + write_acv + .name(name() + ".write_acv") + .desc("DTB write access violations") + ; + + write_accesses + .name(name() + ".write_accesses") + .desc("DTB write accesses") + ; + + hits + .name(name() + ".hits") + .desc("DTB hits") + ; + + misses + .name(name() + ".misses") + .desc("DTB misses") + ; + + acv + .name(name() + ".acv") + .desc("DTB access violations") + ; + + accesses + .name(name() + ".accesses") + .desc("DTB accesses") + ; + + hits = read_hits + write_hits; + misses = read_misses + write_misses; + acv = read_acv + write_acv; + accesses = read_accesses + write_accesses; + } - AlphaISA::mode_type mode = - (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)); + Fault + DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const + { + Addr pc = tc->readPC(); + mode_type mode = + (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)); - /** - * Check for alignment faults - */ - if (req->getVaddr() & (req->getSize() - 1)) { - DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), - req->getSize()); - uint64_t flags = write ? MM_STAT_WR_MASK : 0; - return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); - } - if (pc & 0x1) { - mode = (req->getFlags() & ALTMODE) ? - (AlphaISA::mode_type)ALT_MODE_AM( - tc->readMiscReg(AlphaISA::IPR_ALT_MODE)) - : AlphaISA::mode_kernel; - } + /** + * Check for alignment faults + */ + if (req->getVaddr() & (req->getSize() - 1)) { + DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), + req->getSize()); + uint64_t flags = write ? MM_STAT_WR_MASK : 0; + return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); + } - if (req->getFlags() & PHYSICAL) { - req->setPaddr(req->getVaddr()); - } else { - // verify that this is a good virtual address - if (!validVirtualAddress(req->getVaddr())) { - if (write) { write_acv++; } else { read_acv++; } - uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | - MM_STAT_BAD_VA_MASK | - MM_STAT_ACV_MASK; - return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); + if (pc & 0x1) { + mode = (req->getFlags() & ALTMODE) ? + (mode_type)ALT_MODE_AM( + tc->readMiscReg(IPR_ALT_MODE)) + : mode_kernel; } - // Check for "superpage" mapping + if (req->getFlags() & PHYSICAL) { + req->setPaddr(req->getVaddr()); + } else { + // verify that this is a good virtual address + if (!validVirtualAddress(req->getVaddr())) { + if (write) { write_acv++; } else { read_acv++; } + uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | + MM_STAT_BAD_VA_MASK | + MM_STAT_ACV_MASK; + return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); + } + + // Check for "superpage" mapping #if ALPHA_TLASER - if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->getVaddr()) == 2) { + if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && + VAddrSpaceEV5(req->getVaddr()) == 2) { #else - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { #endif - // only valid in kernel mode - if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) != - AlphaISA::mode_kernel) { - if (write) { write_acv++; } else { read_acv++; } - uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | - MM_STAT_ACV_MASK); - return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); - } + // only valid in kernel mode + if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) != + mode_kernel) { + if (write) { write_acv++; } else { read_acv++; } + uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | + MM_STAT_ACV_MASK); + return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); + } - req->setPaddr(req->getVaddr() & PAddrImplMask); + req->setPaddr(req->getVaddr() & PAddrImplMask); #if !ALPHA_TLASER - // sign extend the physical address properly - if (req->getPaddr() & PAddrUncachedBit40) - req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); - else - req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); + // sign extend the physical address properly + if (req->getPaddr() & PAddrUncachedBit40) + req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); + else + req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); #endif - } else { - if (write) - write_accesses++; - else - read_accesses++; - - int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); - - // not a physical address: need to look up pte - AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), - asn); - - if (!pte) { - // page fault - if (write) { write_misses++; } else { read_misses++; } - uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | - MM_STAT_DTB_MISS_MASK; - return (req->getFlags() & VPTE) ? - (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), - flags)) : - (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), - flags)); - } - - req->setPaddr((pte->ppn << AlphaISA::PageShift) + - AlphaISA::VAddr(req->getVaddr()).offset()); - - if (write) { - if (!(pte->xwe & MODE2MASK(mode))) { - // declare the instruction access fault - write_acv++; - uint64_t flags = MM_STAT_WR_MASK | - MM_STAT_ACV_MASK | - (pte->fonw ? MM_STAT_FONW_MASK : 0); - return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); - } - if (pte->fonw) { - write_acv++; - uint64_t flags = MM_STAT_WR_MASK | - MM_STAT_FONW_MASK; - return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); - } } else { - if (!(pte->xre & MODE2MASK(mode))) { - read_acv++; - uint64_t flags = MM_STAT_ACV_MASK | - (pte->fonr ? MM_STAT_FONR_MASK : 0); - return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); + if (write) + write_accesses++; + else + read_accesses++; + + int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN)); + + // not a physical address: need to look up pte + PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), + asn); + + if (!pte) { + // page fault + if (write) { write_misses++; } else { read_misses++; } + uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | + MM_STAT_DTB_MISS_MASK; + return (req->getFlags() & VPTE) ? + (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), + flags)) : + (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), + flags)); } - if (pte->fonr) { - read_acv++; - uint64_t flags = MM_STAT_FONR_MASK; - return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); + + req->setPaddr((pte->ppn << PageShift) + + VAddr(req->getVaddr()).offset()); + + if (write) { + if (!(pte->xwe & MODE2MASK(mode))) { + // declare the instruction access fault + write_acv++; + uint64_t flags = MM_STAT_WR_MASK | + MM_STAT_ACV_MASK | + (pte->fonw ? MM_STAT_FONW_MASK : 0); + return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); + } + if (pte->fonw) { + write_acv++; + uint64_t flags = MM_STAT_WR_MASK | + MM_STAT_FONW_MASK; + return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); + } + } else { + if (!(pte->xre & MODE2MASK(mode))) { + read_acv++; + uint64_t flags = MM_STAT_ACV_MASK | + (pte->fonr ? MM_STAT_FONR_MASK : 0); + return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); + } + if (pte->fonr) { + read_acv++; + uint64_t flags = MM_STAT_FONR_MASK; + return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); + } } } + + if (write) + write_hits++; + else + read_hits++; } - if (write) - write_hits++; - else - read_hits++; + // check that the physical address is ok (catch bad physical addresses) + if (req->getPaddr() & ~PAddrImplMask) + return genMachineCheckFault(); + + return checkCacheability(req); } - // check that the physical address is ok (catch bad physical addresses) - if (req->getPaddr() & ~PAddrImplMask) - return genMachineCheckFault(); + PTE & + TLB::index(bool advance) + { + PTE *pte = &table[nlu]; - return checkCacheability(req); -} + if (advance) + nextnlu(); -AlphaISA::PTE & -AlphaTLB::index(bool advance) -{ - AlphaISA::PTE *pte = &table[nlu]; + return *pte; + } - if (advance) - nextnlu(); + DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) - return *pte; -} + BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) -DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB) + Param size; -BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) + END_DECLARE_SIM_OBJECT_PARAMS(ITB) - Param size; + BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) -END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) + INIT_PARAM_DFLT(size, "TLB size", 48) -BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB) + END_INIT_SIM_OBJECT_PARAMS(ITB) - INIT_PARAM_DFLT(size, "TLB size", 48) - -END_INIT_SIM_OBJECT_PARAMS(AlphaITB) + CREATE_SIM_OBJECT(ITB) + { + return new ITB(getInstanceName(), size); + } -CREATE_SIM_OBJECT(AlphaITB) -{ - return new AlphaITB(getInstanceName(), size); -} + REGISTER_SIM_OBJECT("AlphaITB", ITB) -REGISTER_SIM_OBJECT("AlphaITB", AlphaITB) + BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) -BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) + Param size; - Param size; + END_DECLARE_SIM_OBJECT_PARAMS(DTB) -END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) + BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) -BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB) + INIT_PARAM_DFLT(size, "TLB size", 64) - INIT_PARAM_DFLT(size, "TLB size", 64) + END_INIT_SIM_OBJECT_PARAMS(DTB) -END_INIT_SIM_OBJECT_PARAMS(AlphaDTB) + CREATE_SIM_OBJECT(DTB) + { + return new DTB(getInstanceName(), size); + } -CREATE_SIM_OBJECT(AlphaDTB) -{ - return new AlphaDTB(getInstanceName(), size); + REGISTER_SIM_OBJECT("AlphaDTB", DTB) } - -REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB) - diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 955460649..ea5ba5539 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -36,6 +36,7 @@ #include "arch/alpha/ev5.hh" #include "arch/alpha/isa_traits.hh" +#include "arch/alpha/pagetable.hh" #include "arch/alpha/utility.hh" #include "arch/alpha/vtophys.hh" #include "base/statistics.hh" @@ -45,82 +46,87 @@ class ThreadContext; -class AlphaTLB : public SimObject +namespace AlphaISA { - protected: - typedef std::multimap PageTable; - PageTable lookupTable; // Quick lookup into page table - - AlphaISA::PTE *table; // the Page Table - int size; // TLB Size - int nlu; // not last used entry (for replacement) - - void nextnlu() { if (++nlu >= size) nlu = 0; } - AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const; - - public: - AlphaTLB(const std::string &name, int size); - virtual ~AlphaTLB(); - - int getsize() const { return size; } - - AlphaISA::PTE &index(bool advance = true); - void insert(Addr vaddr, AlphaISA::PTE &pte); - - void flushAll(); - void flushProcesses(); - void flushAddr(Addr addr, uint8_t asn); - - // static helper functions... really EV5 VM traits - static bool validVirtualAddress(Addr vaddr) { - // unimplemented bits must be all 0 or all 1 - Addr unimplBits = vaddr & EV5::VAddrUnImplMask; - return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); - } - - static Fault checkCacheability(RequestPtr &req); - - // Checkpointing - virtual void serialize(std::ostream &os); - virtual void unserialize(Checkpoint *cp, const std::string §ion); -}; - -class AlphaITB : public AlphaTLB -{ - protected: - mutable Stats::Scalar<> hits; - mutable Stats::Scalar<> misses; - mutable Stats::Scalar<> acv; - mutable Stats::Formula accesses; - - public: - AlphaITB(const std::string &name, int size); - virtual void regStats(); - - Fault translate(RequestPtr &req, ThreadContext *tc) const; -}; - -class AlphaDTB : public AlphaTLB -{ - protected: - mutable Stats::Scalar<> read_hits; - mutable Stats::Scalar<> read_misses; - mutable Stats::Scalar<> read_acv; - mutable Stats::Scalar<> read_accesses; - mutable Stats::Scalar<> write_hits; - mutable Stats::Scalar<> write_misses; - mutable Stats::Scalar<> write_acv; - mutable Stats::Scalar<> write_accesses; - Stats::Formula hits; - Stats::Formula misses; - Stats::Formula acv; - Stats::Formula accesses; - - public: - AlphaDTB(const std::string &name, int size); - virtual void regStats(); - - Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const; -}; + class PTE; + + class TLB : public SimObject + { + protected: + typedef std::multimap PageTable; + PageTable lookupTable; // Quick lookup into page table + + PTE *table; // the Page Table + int size; // TLB Size + int nlu; // not last used entry (for replacement) + + void nextnlu() { if (++nlu >= size) nlu = 0; } + PTE *lookup(Addr vpn, uint8_t asn) const; + + public: + TLB(const std::string &name, int size); + virtual ~TLB(); + + int getsize() const { return size; } + + PTE &index(bool advance = true); + void insert(Addr vaddr, PTE &pte); + + void flushAll(); + void flushProcesses(); + void flushAddr(Addr addr, uint8_t asn); + + // static helper functions... really EV5 VM traits + static bool validVirtualAddress(Addr vaddr) { + // unimplemented bits must be all 0 or all 1 + Addr unimplBits = vaddr & EV5::VAddrUnImplMask; + return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); + } + + static Fault checkCacheability(RequestPtr &req); + + // Checkpointing + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); + }; + + class ITB : public TLB + { + protected: + mutable Stats::Scalar<> hits; + mutable Stats::Scalar<> misses; + mutable Stats::Scalar<> acv; + mutable Stats::Formula accesses; + + public: + ITB(const std::string &name, int size); + virtual void regStats(); + + Fault translate(RequestPtr &req, ThreadContext *tc) const; + }; + + class DTB : public TLB + { + protected: + mutable Stats::Scalar<> read_hits; + mutable Stats::Scalar<> read_misses; + mutable Stats::Scalar<> read_acv; + mutable Stats::Scalar<> read_accesses; + mutable Stats::Scalar<> write_hits; + mutable Stats::Scalar<> write_misses; + mutable Stats::Scalar<> write_acv; + mutable Stats::Scalar<> write_accesses; + Stats::Formula hits; + Stats::Formula misses; + Stats::Formula acv; + Stats::Formula accesses; + + public: + DTB(const std::string &name, int size); + virtual void regStats(); + + Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const; + }; +} #endif // __ALPHA_MEMORY_HH__ -- cgit v1.2.3 From 038217049a952a67f29b79c416a35d89fea31f70 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 03:37:01 -0500 Subject: Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions. --HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9 --- src/arch/alpha/isa/decoder.isa | 8 ++++---- src/arch/alpha/isa/main.isa | 5 +++-- src/arch/alpha/isa_traits.hh | 3 ++- src/arch/alpha/regfile.hh | 2 ++ 4 files changed, 11 insertions(+), 7 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 5bd19b677..93b941d72 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -661,12 +661,12 @@ decode OPCODE default Unknown::unknown() { #if FULL_SYSTEM format BasicOperate { 0xe000: rc({{ - Ra = xc->readIntrFlag(); - xc->setIntrFlag(0); + Ra = IntrFlag; + IntrFlag = 0; }}, IsNonSpeculative, IsUnverifiable); 0xf000: rs({{ - Ra = xc->readIntrFlag(); - xc->setIntrFlag(1); + Ra = IntrFlag; + IntrFlag = 1; }}, IsNonSpeculative, IsUnverifiable); } #else diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 2024b1117..1df6ac603 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -183,8 +183,9 @@ def operands {{ 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), - 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1), - 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1), + 'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1), + 'FPCR': ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1), + 'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1), # The next two are hacks for non-full-system call-pal emulation 'R0': ('IntReg', 'uq', '0', None, 1), 'R16': ('IntReg', 'uq', '16', None, 1), diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index 4f439b8df..66cb21235 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -54,7 +54,8 @@ namespace AlphaISA Uniq_DepTag = 73, Lock_Flag_DepTag = 74, Lock_Addr_DepTag = 75, - IPR_Base_DepTag = 76 + Intr_Flag_DepTag = 76, + IPR_Base_DepTag = 77 }; StaticInstPtr decodeInst(ExtMachInst); diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 43b48a0ab..ea6fc67b2 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -109,6 +109,7 @@ namespace AlphaISA uint64_t uniq; // process-unique register bool lock_flag; // lock flag for LL/SC Addr lock_addr; // lock address for LL/SC + int intr_flag; public: MiscReg readReg(int misc_reg); @@ -131,6 +132,7 @@ namespace AlphaISA fpcr = uniq = 0; lock_flag = 0; lock_addr = 0; + intr_flag = 0; } void serialize(std::ostream &os); -- cgit v1.2.3 From eab445e1bc6178bdbd0f4b5fcd5746a84687de65 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 03:44:39 -0500 Subject: Get rid of old, commented out code. --HG-- extra : convert_revision : 46e9f26917efab642b80ea9e4303ec95d43d935e --- src/arch/sparc/faults.cc | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 2c8da44c5..567ca5f5c 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -359,21 +359,6 @@ void SparcFault::invoke(ThreadContext * tc) countStat()++; //Use the SPARC trap state machine - /*// exception restart address - if (setRestartAddress() || !tc->inPalMode()) - tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc); - - if (skipFaultingInstruction()) { - // traps... skip faulting instruction. - tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, - tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); - } - - if (!tc->inPalMode()) - AlphaISA::swap_palshadow(&(tc->regs), true); - - tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); - tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/ } #endif -- cgit v1.2.3 From ece796ab8af23705f3f4d7bd12ee623f3961c99e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 16:02:28 -0500 Subject: Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR. --HG-- extra : convert_revision : dd235261e7086d6667b1b2bdc4a81b2573e21d53 --- src/arch/alpha/SConscript | 1 + src/arch/alpha/ev5.cc | 306 ++++++++++++++++++++--------------------- src/arch/alpha/ipr.cc | 140 +++++++++++++++++++ src/arch/alpha/ipr.hh | 228 ++++++++++++++++++++++++++++++ src/arch/alpha/isa/decoder.isa | 16 ++- src/arch/alpha/isa/main.isa | 1 + src/arch/alpha/isa_traits.hh | 95 +------------ src/arch/alpha/regfile.hh | 8 +- 8 files changed, 545 insertions(+), 250 deletions(-) create mode 100644 src/arch/alpha/ipr.cc create mode 100644 src/arch/alpha/ipr.hh (limited to 'src/arch') diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 216c88cc7..9a5680649 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -56,6 +56,7 @@ full_system_sources = Split(''' tlb.cc arguments.cc ev5.cc + ipr.cc osfpal.cc stacktrace.cc vtophys.cc diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 7595423c3..56dadd6b1 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -62,7 +62,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId) AlphaFault *reset = new ResetFault; - tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect()); + tc->setPC(tc->readMiscReg(MISCREG_IPR_PAL_BASE) + reset->vect()); tc->setNextPC(tc->readPC() + sizeof(MachInst)); delete reset; @@ -79,9 +79,9 @@ AlphaISA::initIPRs(ThreadContext *tc, int cpuId) tc->setMiscReg(i, 0); } - tc->setMiscReg(IPR_PAL_BASE, PalBase); - tc->setMiscReg(IPR_MCSR, 0x6); - tc->setMiscReg(IPR_PALtemp16, cpuId); + tc->setMiscReg(MISCREG_IPR_PAL_BASE, PalBase); + tc->setMiscReg(MISCREG_IPR_MCSR, 0x6); + tc->setMiscReg(MISCREG_IPR_PALtemp16, cpuId); } @@ -96,13 +96,13 @@ AlphaISA::processInterrupts(CPU *cpu) cpu->checkInterrupts = false; - if (cpu->readMiscReg(IPR_ASTRR)) + if (cpu->readMiscReg(MISCREG_IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (cpu->readMiscReg(IPR_SIRR)) { + if (cpu->readMiscReg(MISCREG_IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { + if (cpu->readMiscReg(MISCREG_IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of the 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -123,12 +123,12 @@ AlphaISA::processInterrupts(CPU *cpu) } } - if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { - cpu->setMiscReg(IPR_ISR, summary); - cpu->setMiscReg(IPR_INTID, ipl); + if (ipl && ipl > cpu->readMiscReg(MISCREG_IPR_IPLR)) { + cpu->setMiscReg(MISCREG_IPR_ISR, summary); + cpu->setMiscReg(MISCREG_IPR_INTID, ipl); cpu->trap(new InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - cpu->readMiscReg(IPR_IPLR), ipl, summary); + cpu->readMiscReg(MISCREG_IPR_IPLR), ipl, summary); } } @@ -150,7 +150,7 @@ SimpleThread::hwrei() if (!inPalMode()) return new UnimplementedOpcodeFault; - setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); + setNextPC(readMiscReg(AlphaISA::MISCREG_IPR_EXC_ADDR)); if (!misspeculating()) { if (kernelStats) @@ -166,13 +166,13 @@ SimpleThread::hwrei() int AlphaISA::MiscRegFile::getInstAsid() { - return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); + return EV5::ITB_ASN_ASN(ipr[MISCREG_IPR_ITB_ASN]); } int AlphaISA::MiscRegFile::getDataAsid() { - return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); + return EV5::DTB_ASN_ASN(ipr[MISCREG_IPR_DTB_ASN]); } AlphaISA::MiscReg @@ -181,71 +181,71 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) uint64_t retval = 0; // return value, default 0 switch (idx) { - case AlphaISA::IPR_PALtemp0: - case AlphaISA::IPR_PALtemp1: - case AlphaISA::IPR_PALtemp2: - case AlphaISA::IPR_PALtemp3: - case AlphaISA::IPR_PALtemp4: - case AlphaISA::IPR_PALtemp5: - case AlphaISA::IPR_PALtemp6: - case AlphaISA::IPR_PALtemp7: - case AlphaISA::IPR_PALtemp8: - case AlphaISA::IPR_PALtemp9: - case AlphaISA::IPR_PALtemp10: - case AlphaISA::IPR_PALtemp11: - case AlphaISA::IPR_PALtemp12: - case AlphaISA::IPR_PALtemp13: - case AlphaISA::IPR_PALtemp14: - case AlphaISA::IPR_PALtemp15: - case AlphaISA::IPR_PALtemp16: - case AlphaISA::IPR_PALtemp17: - case AlphaISA::IPR_PALtemp18: - case AlphaISA::IPR_PALtemp19: - case AlphaISA::IPR_PALtemp20: - case AlphaISA::IPR_PALtemp21: - case AlphaISA::IPR_PALtemp22: - case AlphaISA::IPR_PALtemp23: - case AlphaISA::IPR_PAL_BASE: - - case AlphaISA::IPR_IVPTBR: - case AlphaISA::IPR_DC_MODE: - case AlphaISA::IPR_MAF_MODE: - case AlphaISA::IPR_ISR: - case AlphaISA::IPR_EXC_ADDR: - case AlphaISA::IPR_IC_PERR_STAT: - case AlphaISA::IPR_DC_PERR_STAT: - case AlphaISA::IPR_MCSR: - case AlphaISA::IPR_ASTRR: - case AlphaISA::IPR_ASTER: - case AlphaISA::IPR_SIRR: - case AlphaISA::IPR_ICSR: - case AlphaISA::IPR_ICM: - case AlphaISA::IPR_DTB_CM: - case AlphaISA::IPR_IPLR: - case AlphaISA::IPR_INTID: - case AlphaISA::IPR_PMCTR: + case AlphaISA::MISCREG_IPR_PALtemp0: + case AlphaISA::MISCREG_IPR_PALtemp1: + case AlphaISA::MISCREG_IPR_PALtemp2: + case AlphaISA::MISCREG_IPR_PALtemp3: + case AlphaISA::MISCREG_IPR_PALtemp4: + case AlphaISA::MISCREG_IPR_PALtemp5: + case AlphaISA::MISCREG_IPR_PALtemp6: + case AlphaISA::MISCREG_IPR_PALtemp7: + case AlphaISA::MISCREG_IPR_PALtemp8: + case AlphaISA::MISCREG_IPR_PALtemp9: + case AlphaISA::MISCREG_IPR_PALtemp10: + case AlphaISA::MISCREG_IPR_PALtemp11: + case AlphaISA::MISCREG_IPR_PALtemp12: + case AlphaISA::MISCREG_IPR_PALtemp13: + case AlphaISA::MISCREG_IPR_PALtemp14: + case AlphaISA::MISCREG_IPR_PALtemp15: + case AlphaISA::MISCREG_IPR_PALtemp16: + case AlphaISA::MISCREG_IPR_PALtemp17: + case AlphaISA::MISCREG_IPR_PALtemp18: + case AlphaISA::MISCREG_IPR_PALtemp19: + case AlphaISA::MISCREG_IPR_PALtemp20: + case AlphaISA::MISCREG_IPR_PALtemp21: + case AlphaISA::MISCREG_IPR_PALtemp22: + case AlphaISA::MISCREG_IPR_PALtemp23: + case AlphaISA::MISCREG_IPR_PAL_BASE: + + case AlphaISA::MISCREG_IPR_IVPTBR: + case AlphaISA::MISCREG_IPR_DC_MODE: + case AlphaISA::MISCREG_IPR_MAF_MODE: + case AlphaISA::MISCREG_IPR_ISR: + case AlphaISA::MISCREG_IPR_EXC_ADDR: + case AlphaISA::MISCREG_IPR_IC_PERR_STAT: + case AlphaISA::MISCREG_IPR_DC_PERR_STAT: + case AlphaISA::MISCREG_IPR_MCSR: + case AlphaISA::MISCREG_IPR_ASTRR: + case AlphaISA::MISCREG_IPR_ASTER: + case AlphaISA::MISCREG_IPR_SIRR: + case AlphaISA::MISCREG_IPR_ICSR: + case AlphaISA::MISCREG_IPR_ICM: + case AlphaISA::MISCREG_IPR_DTB_CM: + case AlphaISA::MISCREG_IPR_IPLR: + case AlphaISA::MISCREG_IPR_INTID: + case AlphaISA::MISCREG_IPR_PMCTR: // no side-effect retval = ipr[idx]; break; - case AlphaISA::IPR_CC: + case AlphaISA::MISCREG_IPR_CC: retval |= ipr[idx] & ULL(0xffffffff00000000); retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); break; - case AlphaISA::IPR_VA: + case AlphaISA::MISCREG_IPR_VA: retval = ipr[idx]; break; - case AlphaISA::IPR_VA_FORM: - case AlphaISA::IPR_MM_STAT: - case AlphaISA::IPR_IFAULT_VA_FORM: - case AlphaISA::IPR_EXC_MASK: - case AlphaISA::IPR_EXC_SUM: + case AlphaISA::MISCREG_IPR_VA_FORM: + case AlphaISA::MISCREG_IPR_MM_STAT: + case AlphaISA::MISCREG_IPR_IFAULT_VA_FORM: + case AlphaISA::MISCREG_IPR_EXC_MASK: + case AlphaISA::MISCREG_IPR_EXC_SUM: retval = ipr[idx]; break; - case AlphaISA::IPR_DTB_PTE: + case AlphaISA::MISCREG_IPR_DTB_PTE: { AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); @@ -260,15 +260,15 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) break; // write only registers - case AlphaISA::IPR_HWINT_CLR: - case AlphaISA::IPR_SL_XMIT: - case AlphaISA::IPR_DC_FLUSH: - case AlphaISA::IPR_IC_FLUSH: - case AlphaISA::IPR_ALT_MODE: - case AlphaISA::IPR_DTB_IA: - case AlphaISA::IPR_DTB_IAP: - case AlphaISA::IPR_ITB_IA: - case AlphaISA::IPR_ITB_IAP: + case AlphaISA::MISCREG_IPR_HWINT_CLR: + case AlphaISA::MISCREG_IPR_SL_XMIT: + case AlphaISA::MISCREG_IPR_DC_FLUSH: + case AlphaISA::MISCREG_IPR_IC_FLUSH: + case AlphaISA::MISCREG_IPR_ALT_MODE: + case AlphaISA::MISCREG_IPR_DTB_IA: + case AlphaISA::MISCREG_IPR_DTB_IAP: + case AlphaISA::MISCREG_IPR_ITB_IA: + case AlphaISA::MISCREG_IPR_ITB_IAP: fault = new UnimplementedOpcodeFault; break; @@ -295,52 +295,52 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) return NoFault; switch (idx) { - case AlphaISA::IPR_PALtemp0: - case AlphaISA::IPR_PALtemp1: - case AlphaISA::IPR_PALtemp2: - case AlphaISA::IPR_PALtemp3: - case AlphaISA::IPR_PALtemp4: - case AlphaISA::IPR_PALtemp5: - case AlphaISA::IPR_PALtemp6: - case AlphaISA::IPR_PALtemp7: - case AlphaISA::IPR_PALtemp8: - case AlphaISA::IPR_PALtemp9: - case AlphaISA::IPR_PALtemp10: - case AlphaISA::IPR_PALtemp11: - case AlphaISA::IPR_PALtemp12: - case AlphaISA::IPR_PALtemp13: - case AlphaISA::IPR_PALtemp14: - case AlphaISA::IPR_PALtemp15: - case AlphaISA::IPR_PALtemp16: - case AlphaISA::IPR_PALtemp17: - case AlphaISA::IPR_PALtemp18: - case AlphaISA::IPR_PALtemp19: - case AlphaISA::IPR_PALtemp20: - case AlphaISA::IPR_PALtemp21: - case AlphaISA::IPR_PALtemp22: - case AlphaISA::IPR_PAL_BASE: - case AlphaISA::IPR_IC_PERR_STAT: - case AlphaISA::IPR_DC_PERR_STAT: - case AlphaISA::IPR_PMCTR: + case AlphaISA::MISCREG_IPR_PALtemp0: + case AlphaISA::MISCREG_IPR_PALtemp1: + case AlphaISA::MISCREG_IPR_PALtemp2: + case AlphaISA::MISCREG_IPR_PALtemp3: + case AlphaISA::MISCREG_IPR_PALtemp4: + case AlphaISA::MISCREG_IPR_PALtemp5: + case AlphaISA::MISCREG_IPR_PALtemp6: + case AlphaISA::MISCREG_IPR_PALtemp7: + case AlphaISA::MISCREG_IPR_PALtemp8: + case AlphaISA::MISCREG_IPR_PALtemp9: + case AlphaISA::MISCREG_IPR_PALtemp10: + case AlphaISA::MISCREG_IPR_PALtemp11: + case AlphaISA::MISCREG_IPR_PALtemp12: + case AlphaISA::MISCREG_IPR_PALtemp13: + case AlphaISA::MISCREG_IPR_PALtemp14: + case AlphaISA::MISCREG_IPR_PALtemp15: + case AlphaISA::MISCREG_IPR_PALtemp16: + case AlphaISA::MISCREG_IPR_PALtemp17: + case AlphaISA::MISCREG_IPR_PALtemp18: + case AlphaISA::MISCREG_IPR_PALtemp19: + case AlphaISA::MISCREG_IPR_PALtemp20: + case AlphaISA::MISCREG_IPR_PALtemp21: + case AlphaISA::MISCREG_IPR_PALtemp22: + case AlphaISA::MISCREG_IPR_PAL_BASE: + case AlphaISA::MISCREG_IPR_IC_PERR_STAT: + case AlphaISA::MISCREG_IPR_DC_PERR_STAT: + case AlphaISA::MISCREG_IPR_PMCTR: // write entire quad w/ no side-effect ipr[idx] = val; break; - case AlphaISA::IPR_CC_CTL: + case AlphaISA::MISCREG_IPR_CC_CTL: // This IPR resets the cycle counter. We assume this only // happens once... let's verify that. assert(ipr[idx] == 0); ipr[idx] = 1; break; - case AlphaISA::IPR_CC: + case AlphaISA::MISCREG_IPR_CC: // This IPR only writes the upper 64 bits. It's ok to write // all 64 here since we mask out the lower 32 in rpcc (see // isa_desc). ipr[idx] = val; break; - case AlphaISA::IPR_PALtemp23: + case AlphaISA::MISCREG_IPR_PALtemp23: // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; @@ -348,23 +348,23 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->context(old, val, tc); break; - case AlphaISA::IPR_DTB_PTE: + case AlphaISA::MISCREG_IPR_DTB_PTE: // write entire quad w/ no side-effect, tag is forthcoming ipr[idx] = val; break; - case AlphaISA::IPR_EXC_ADDR: + case AlphaISA::MISCREG_IPR_EXC_ADDR: // second least significant bit in PC is always zero ipr[idx] = val & ~2; break; - case AlphaISA::IPR_ASTRR: - case AlphaISA::IPR_ASTER: + case AlphaISA::MISCREG_IPR_ASTRR: + case AlphaISA::MISCREG_IPR_ASTER: // only write least significant four bits - privilege mask ipr[idx] = val & 0xf; break; - case AlphaISA::IPR_IPLR: + case AlphaISA::MISCREG_IPR_IPLR: #ifdef DEBUG if (break_ipl != -1 && break_ipl == (val & 0x1f)) debug_break(); @@ -376,7 +376,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->swpipl(ipr[idx]); break; - case AlphaISA::IPR_DTB_CM: + case AlphaISA::MISCREG_IPR_DTB_CM: if (val & 0x18) { if (tc->getKernelStats()) tc->getKernelStats()->mode(Kernel::user, tc); @@ -385,121 +385,121 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->mode(Kernel::kernel, tc); } - case AlphaISA::IPR_ICM: + case AlphaISA::MISCREG_IPR_ICM: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case AlphaISA::IPR_ALT_MODE: + case AlphaISA::MISCREG_IPR_ALT_MODE: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case AlphaISA::IPR_MCSR: + case AlphaISA::MISCREG_IPR_MCSR: // more here after optimization... ipr[idx] = val; break; - case AlphaISA::IPR_SIRR: + case AlphaISA::MISCREG_IPR_SIRR: // only write software interrupt mask ipr[idx] = val & 0x7fff0; break; - case AlphaISA::IPR_ICSR: + case AlphaISA::MISCREG_IPR_ICSR: ipr[idx] = val & ULL(0xffffff0300); break; - case AlphaISA::IPR_IVPTBR: - case AlphaISA::IPR_MVPTBR: + case AlphaISA::MISCREG_IPR_IVPTBR: + case AlphaISA::MISCREG_IPR_MVPTBR: ipr[idx] = val & ULL(0xffffffffc0000000); break; - case AlphaISA::IPR_DC_TEST_CTL: + case AlphaISA::MISCREG_IPR_DC_TEST_CTL: ipr[idx] = val & 0x1ffb; break; - case AlphaISA::IPR_DC_MODE: - case AlphaISA::IPR_MAF_MODE: + case AlphaISA::MISCREG_IPR_DC_MODE: + case AlphaISA::MISCREG_IPR_MAF_MODE: ipr[idx] = val & 0x3f; break; - case AlphaISA::IPR_ITB_ASN: + case AlphaISA::MISCREG_IPR_ITB_ASN: ipr[idx] = val & 0x7f0; break; - case AlphaISA::IPR_DTB_ASN: + case AlphaISA::MISCREG_IPR_DTB_ASN: ipr[idx] = val & ULL(0xfe00000000000000); break; - case AlphaISA::IPR_EXC_SUM: - case AlphaISA::IPR_EXC_MASK: + case AlphaISA::MISCREG_IPR_EXC_SUM: + case AlphaISA::MISCREG_IPR_EXC_MASK: // any write to this register clears it ipr[idx] = 0; break; - case AlphaISA::IPR_INTID: - case AlphaISA::IPR_SL_RCV: - case AlphaISA::IPR_MM_STAT: - case AlphaISA::IPR_ITB_PTE_TEMP: - case AlphaISA::IPR_DTB_PTE_TEMP: + case AlphaISA::MISCREG_IPR_INTID: + case AlphaISA::MISCREG_IPR_SL_RCV: + case AlphaISA::MISCREG_IPR_MM_STAT: + case AlphaISA::MISCREG_IPR_ITB_PTE_TEMP: + case AlphaISA::MISCREG_IPR_DTB_PTE_TEMP: // read-only registers return new UnimplementedOpcodeFault; - case AlphaISA::IPR_HWINT_CLR: - case AlphaISA::IPR_SL_XMIT: - case AlphaISA::IPR_DC_FLUSH: - case AlphaISA::IPR_IC_FLUSH: + case AlphaISA::MISCREG_IPR_HWINT_CLR: + case AlphaISA::MISCREG_IPR_SL_XMIT: + case AlphaISA::MISCREG_IPR_DC_FLUSH: + case AlphaISA::MISCREG_IPR_IC_FLUSH: // the following are write only ipr[idx] = val; break; - case AlphaISA::IPR_DTB_IA: + case AlphaISA::MISCREG_IPR_DTB_IA: // really a control write ipr[idx] = 0; tc->getDTBPtr()->flushAll(); break; - case AlphaISA::IPR_DTB_IAP: + case AlphaISA::MISCREG_IPR_DTB_IAP: // really a control write ipr[idx] = 0; tc->getDTBPtr()->flushProcesses(); break; - case AlphaISA::IPR_DTB_IS: + case AlphaISA::MISCREG_IPR_DTB_IS: // really a control write ipr[idx] = val; tc->getDTBPtr()->flushAddr(val, - DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + DTB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_DTB_ASN])); break; - case AlphaISA::IPR_DTB_TAG: { + case AlphaISA::MISCREG_IPR_DTB_TAG: { struct AlphaISA::PTE pte; // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) + if (DTB_PTE_GH(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]) != 0) panic("PTE GH field != 0"); // write entire quad ipr[idx] = val; // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); + pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); + pte.xre = DTB_PTE_XRE(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); + pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); + pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); + pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); + pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); + pte.asn = DTB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_DTB_ASN]); // insert new TAG/PTE value into data TLB tc->getDTBPtr()->insert(val, pte); } break; - case AlphaISA::IPR_ITB_PTE: { + case AlphaISA::MISCREG_IPR_ITB_PTE: { struct AlphaISA::PTE pte; // FIXME: granularity hints NYI... @@ -516,33 +516,33 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) pte.fonr = ITB_PTE_FONR(val); pte.fonw = ITB_PTE_FONW(val); pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); + pte.asn = ITB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_ITB_ASN]); // insert new TAG/PTE value into data TLB - tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); + tc->getITBPtr()->insert(ipr[AlphaISA::MISCREG_IPR_ITB_TAG], pte); } break; - case AlphaISA::IPR_ITB_IA: + case AlphaISA::MISCREG_IPR_ITB_IA: // really a control write ipr[idx] = 0; tc->getITBPtr()->flushAll(); break; - case AlphaISA::IPR_ITB_IAP: + case AlphaISA::MISCREG_IPR_ITB_IAP: // really a control write ipr[idx] = 0; tc->getITBPtr()->flushProcesses(); break; - case AlphaISA::IPR_ITB_IS: + case AlphaISA::MISCREG_IPR_ITB_IS: // really a control write ipr[idx] = val; tc->getITBPtr()->flushAddr(val, - ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); + ITB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_ITB_ASN])); break; default: diff --git a/src/arch/alpha/ipr.cc b/src/arch/alpha/ipr.cc new file mode 100644 index 000000000..50086a845 --- /dev/null +++ b/src/arch/alpha/ipr.cc @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include +#include + +#include "arch/alpha/ipr.hh" + +namespace AlphaISA +{ + md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = + { + //Write only + IPR_HWINT_CLR, // H/W interrupt clear register + IPR_SL_XMIT, // serial line transmit register + IPR_DC_FLUSH, + IPR_IC_FLUSH, // instruction cache flush control + IPR_ALT_MODE, // alternate mode register + IPR_DTB_IA, // DTLB invalidate all register + IPR_DTB_IAP, // DTLB invalidate all process register + IPR_ITB_IA, // ITLB invalidate all register + IPR_ITB_IAP, // ITLB invalidate all process register + + //Read only + IPR_INTID, // interrupt ID register + IPR_SL_RCV, // serial line receive register + IPR_MM_STAT, // data MMU fault status register + IPR_ITB_PTE_TEMP, // ITLB page table entry temp register + IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register + + IPR_ISR, // interrupt summary register + IPR_ITB_TAG, // ITLB tag register + IPR_ITB_PTE, // ITLB page table entry register + IPR_ITB_ASN, // ITLB address space register + IPR_ITB_IS, // ITLB invalidate select register + IPR_SIRR, // software interrupt request register + IPR_ASTRR, // asynchronous system trap request register + IPR_ASTER, // asynchronous system trap enable register + IPR_EXC_ADDR, // exception address register + IPR_EXC_SUM, // exception summary register + IPR_EXC_MASK, // exception mask register + IPR_PAL_BASE, // PAL base address register + IPR_ICM, // instruction current mode + IPR_IPLR, // interrupt priority level register + IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register + IPR_IVPTBR, // virtual page table base register + IPR_ICSR, // instruction control and status register + IPR_IC_PERR_STAT, // inst cache parity error status register + IPR_PMCTR, // performance counter register + + // PAL temporary registers... + // register meanings gleaned from osfpal.s source code + IPR_PALtemp0, // local scratch + IPR_PALtemp1, // local scratch + IPR_PALtemp2, // entUna + IPR_PALtemp3, // CPU specific impure area pointer + IPR_PALtemp4, // memory management temp + IPR_PALtemp5, // memory management temp + IPR_PALtemp6, // memory management temp + IPR_PALtemp7, // entIF + IPR_PALtemp8, // intmask + IPR_PALtemp9, // entSys + IPR_PALtemp10, // ?? + IPR_PALtemp11, // entInt + IPR_PALtemp12, // entArith + IPR_PALtemp13, // reserved for platform specific PAL + IPR_PALtemp14, // reserved for platform specific PAL + IPR_PALtemp15, // reserved for platform specific PAL + IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> + IPR_PALtemp17, // sysval + IPR_PALtemp18, // usp + IPR_PALtemp19, // ksp + IPR_PALtemp20, // PTBR + IPR_PALtemp21, // entMM + IPR_PALtemp22, // kgp + IPR_PALtemp23, // PCBB + + IPR_DTB_ASN, // DTLB address space number register + IPR_DTB_CM, // DTLB current mode register + IPR_DTB_TAG, // DTLB tag register + IPR_DTB_PTE, // DTLB page table entry register + + IPR_VA, // fault virtual address register + IPR_VA_FORM, // formatted virtual address register + IPR_MVPTBR, // MTU virtual page table base register + IPR_DTB_IS, // DTLB invalidate single register + IPR_CC, // cycle counter register + IPR_CC_CTL, // cycle counter control register + IPR_MCSR, // MTU control register + + IPR_DC_PERR_STAT, // Dcache parity error status register + IPR_DC_TEST_CTL, // Dcache test tag control register + IPR_DC_TEST_TAG, // Dcache test tag register + IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register + IPR_DC_MODE, // Dcache mode register + IPR_MAF_MODE // miss address file mode register + }; + + int IprToMiscRegIndex[MaxInternalProcRegs]; + + void initializeIprTable() + { + static bool initialized = false; + if(initialized) + return; + + memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int)); + + for(int x = 0; x < NumInternalProcRegs; x++) + IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x; + } +} + diff --git a/src/arch/alpha/ipr.hh b/src/arch/alpha/ipr.hh new file mode 100644 index 000000000..dba0733ba --- /dev/null +++ b/src/arch/alpha/ipr.hh @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + */ + +#ifndef __ARCH_ALPHA_IPR_HH__ +#define __ARCH_ALPHA_IPR_HH__ + +namespace AlphaISA +{ + //////////////////////////////////////////////////////////////////////// + // + // Internal Processor Reigsters + // + enum md_ipr_names + { + IPR_ISR = 0x100, // interrupt summary register + IPR_ITB_TAG = 0x101, // ITLB tag register + IPR_ITB_PTE = 0x102, // ITLB page table entry register + IPR_ITB_ASN = 0x103, // ITLB address space register + IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register + IPR_ITB_IA = 0x105, // ITLB invalidate all register + IPR_ITB_IAP = 0x106, // ITLB invalidate all process register + IPR_ITB_IS = 0x107, // ITLB invalidate select register + IPR_SIRR = 0x108, // software interrupt request register + IPR_ASTRR = 0x109, // asynchronous system trap request register + IPR_ASTER = 0x10a, // asynchronous system trap enable register + IPR_EXC_ADDR = 0x10b, // exception address register + IPR_EXC_SUM = 0x10c, // exception summary register + IPR_EXC_MASK = 0x10d, // exception mask register + IPR_PAL_BASE = 0x10e, // PAL base address register + IPR_ICM = 0x10f, // instruction current mode + IPR_IPLR = 0x110, // interrupt priority level register + IPR_INTID = 0x111, // interrupt ID register + IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register + IPR_IVPTBR = 0x113, // virtual page table base register + IPR_HWINT_CLR = 0x115, // H/W interrupt clear register + IPR_SL_XMIT = 0x116, // serial line transmit register + IPR_SL_RCV = 0x117, // serial line receive register + IPR_ICSR = 0x118, // instruction control and status register + IPR_IC_FLUSH = 0x119, // instruction cache flush control + IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register + IPR_PMCTR = 0x11c, // performance counter register + + // PAL temporary registers... + // register meanings gleaned from osfpal.s source code + IPR_PALtemp0 = 0x140, // local scratch + IPR_PALtemp1 = 0x141, // local scratch + IPR_PALtemp2 = 0x142, // entUna + IPR_PALtemp3 = 0x143, // CPU specific impure area pointer + IPR_PALtemp4 = 0x144, // memory management temp + IPR_PALtemp5 = 0x145, // memory management temp + IPR_PALtemp6 = 0x146, // memory management temp + IPR_PALtemp7 = 0x147, // entIF + IPR_PALtemp8 = 0x148, // intmask + IPR_PALtemp9 = 0x149, // entSys + IPR_PALtemp10 = 0x14a, // ?? + IPR_PALtemp11 = 0x14b, // entInt + IPR_PALtemp12 = 0x14c, // entArith + IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL + IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL + IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL + IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> + IPR_PALtemp17 = 0x151, // sysval + IPR_PALtemp18 = 0x152, // usp + IPR_PALtemp19 = 0x153, // ksp + IPR_PALtemp20 = 0x154, // PTBR + IPR_PALtemp21 = 0x155, // entMM + IPR_PALtemp22 = 0x156, // kgp + IPR_PALtemp23 = 0x157, // PCBB + + IPR_DTB_ASN = 0x200, // DTLB address space number register + IPR_DTB_CM = 0x201, // DTLB current mode register + IPR_DTB_TAG = 0x202, // DTLB tag register + IPR_DTB_PTE = 0x203, // DTLB page table entry register + IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register + + IPR_MM_STAT = 0x205, // data MMU fault status register + IPR_VA = 0x206, // fault virtual address register + IPR_VA_FORM = 0x207, // formatted virtual address register + IPR_MVPTBR = 0x208, // MTU virtual page table base register + IPR_DTB_IAP = 0x209, // DTLB invalidate all process register + IPR_DTB_IA = 0x20a, // DTLB invalidate all register + IPR_DTB_IS = 0x20b, // DTLB invalidate single register + IPR_ALT_MODE = 0x20c, // alternate mode register + IPR_CC = 0x20d, // cycle counter register + IPR_CC_CTL = 0x20e, // cycle counter control register + IPR_MCSR = 0x20f, // MTU control register + + IPR_DC_FLUSH = 0x210, + IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register + IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register + IPR_DC_TEST_TAG = 0x214, // Dcache test tag register + IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register + IPR_DC_MODE = 0x216, // Dcache mode register + IPR_MAF_MODE = 0x217, // miss address file mode register + + MaxInternalProcRegs // number of IPR registers + }; + + enum MiscRegIpr + { + //Write only + MinWriteOnlyIpr, + MISCREG_IPR_HWINT_CLR = MinWriteOnlyIpr, + MISCREG_IPR_SL_XMIT, + MISCREG_IPR_DC_FLUSH, + MISCREG_IPR_IC_FLUSH, + MISCREG_IPR_ALT_MODE, + MISCREG_IPR_DTB_IA, + MISCREG_IPR_DTB_IAP, + MISCREG_IPR_ITB_IA, + MaxWriteOnlyIpr, + MISCREG_IPR_ITB_IAP = MaxWriteOnlyIpr, + + //Read only + MinReadOnlyIpr, + MISCREG_IPR_INTID = MinReadOnlyIpr, + MISCREG_IPR_SL_RCV, + MISCREG_IPR_MM_STAT, + MISCREG_IPR_ITB_PTE_TEMP, + MaxReadOnlyIpr, + MISCREG_IPR_DTB_PTE_TEMP = MaxReadOnlyIpr, + + MISCREG_IPR_ISR, + MISCREG_IPR_ITB_TAG, + MISCREG_IPR_ITB_PTE, + MISCREG_IPR_ITB_ASN, + MISCREG_IPR_ITB_IS, + MISCREG_IPR_SIRR, + MISCREG_IPR_ASTRR, + MISCREG_IPR_ASTER, + MISCREG_IPR_EXC_ADDR, + MISCREG_IPR_EXC_SUM, + MISCREG_IPR_EXC_MASK, + MISCREG_IPR_PAL_BASE, + MISCREG_IPR_ICM, + MISCREG_IPR_IPLR, + MISCREG_IPR_IFAULT_VA_FORM, + MISCREG_IPR_IVPTBR, + MISCREG_IPR_ICSR, + MISCREG_IPR_IC_PERR_STAT, + MISCREG_IPR_PMCTR, + + // PAL temporary registers... + // register meanings gleaned from osfpal.s source code + MISCREG_IPR_PALtemp0, + MISCREG_IPR_PALtemp1, + MISCREG_IPR_PALtemp2, + MISCREG_IPR_PALtemp3, + MISCREG_IPR_PALtemp4, + MISCREG_IPR_PALtemp5, + MISCREG_IPR_PALtemp6, + MISCREG_IPR_PALtemp7, + MISCREG_IPR_PALtemp8, + MISCREG_IPR_PALtemp9, + MISCREG_IPR_PALtemp10, + MISCREG_IPR_PALtemp11, + MISCREG_IPR_PALtemp12, + MISCREG_IPR_PALtemp13, + MISCREG_IPR_PALtemp14, + MISCREG_IPR_PALtemp15, + MISCREG_IPR_PALtemp16, + MISCREG_IPR_PALtemp17, + MISCREG_IPR_PALtemp18, + MISCREG_IPR_PALtemp19, + MISCREG_IPR_PALtemp20, + MISCREG_IPR_PALtemp21, + MISCREG_IPR_PALtemp22, + MISCREG_IPR_PALtemp23, + + MISCREG_IPR_DTB_ASN, + MISCREG_IPR_DTB_CM, + MISCREG_IPR_DTB_TAG, + MISCREG_IPR_DTB_PTE, + + MISCREG_IPR_VA, + MISCREG_IPR_VA_FORM, + MISCREG_IPR_MVPTBR, + MISCREG_IPR_DTB_IS, + MISCREG_IPR_CC, + MISCREG_IPR_CC_CTL, + MISCREG_IPR_MCSR, + + MISCREG_IPR_DC_PERR_STAT, + MISCREG_IPR_DC_TEST_CTL, + MISCREG_IPR_DC_TEST_TAG, + MISCREG_IPR_DC_TEST_TAG_TEMP, + MISCREG_IPR_DC_MODE, + MISCREG_IPR_MAF_MODE, + + NumInternalProcRegs // number of IPR registers + }; + + + extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs]; + extern int IprToMiscRegIndex[MaxInternalProcRegs]; + + void initializeIprTable(); +} + +#endif diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 93b941d72..852f483e0 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -745,7 +745,13 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mfpr(); format HwMoveIPR { 1: hw_mfpr({{ - Ra = xc->readMiscRegWithEffect(ipr_index, fault); + int miscRegIndex = IprToMiscRegIndex[ipr_index]; + if(miscRegIndex < 0 || + (miscRegIndex >= MinWriteOnlyIpr && + miscRegIndex <= MaxWriteOnlyIpr)) + fault = new UnimplementedOpcodeFault; + else + Ra = xc->readMiscRegWithEffect(ipr_index, fault); }}, IsIprAccess); } } @@ -754,7 +760,13 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mtpr(); format HwMoveIPR { 1: hw_mtpr({{ - xc->setMiscRegWithEffect(ipr_index, Ra); + int miscRegIndex = IprToMiscRegIndex[ipr_index]; + if(miscRegIndex < 0 || + (miscRegIndex >= MinReadOnlyIpr && + miscRegIndex <= MaxWriteOnlyIpr)) + fault = new UnimplementedOpcodeFault; + else + xc->setMiscRegWithEffect(ipr_index, Ra); if (traceData) { traceData->setData(Ra); } }}, IsIprAccess); } diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 1df6ac603..06d3e8243 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -71,6 +71,7 @@ output exec {{ #if FULL_SYSTEM #include "sim/pseudo_inst.hh" #endif +#include "arch/alpha/ipr.hh" #include "base/fenv.hh" #include "config/ss_compatible_fp.hh" #include "cpu/base.hh" diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index 66cb21235..a919a4a1f 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -34,6 +34,7 @@ namespace LittleEndianGuest {} +#include "arch/alpha/ipr.hh" #include "arch/alpha/types.hh" #include "config/full_system.hh" #include "sim/host.hh" @@ -132,100 +133,6 @@ namespace AlphaISA #endif -#if FULL_SYSTEM - //////////////////////////////////////////////////////////////////////// - // - // Internal Processor Reigsters - // - enum md_ipr_names - { - IPR_ISR = 0x100, // interrupt summary register - IPR_ITB_TAG = 0x101, // ITLB tag register - IPR_ITB_PTE = 0x102, // ITLB page table entry register - IPR_ITB_ASN = 0x103, // ITLB address space register - IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register - IPR_ITB_IA = 0x105, // ITLB invalidate all register - IPR_ITB_IAP = 0x106, // ITLB invalidate all process register - IPR_ITB_IS = 0x107, // ITLB invalidate select register - IPR_SIRR = 0x108, // software interrupt request register - IPR_ASTRR = 0x109, // asynchronous system trap request register - IPR_ASTER = 0x10a, // asynchronous system trap enable register - IPR_EXC_ADDR = 0x10b, // exception address register - IPR_EXC_SUM = 0x10c, // exception summary register - IPR_EXC_MASK = 0x10d, // exception mask register - IPR_PAL_BASE = 0x10e, // PAL base address register - IPR_ICM = 0x10f, // instruction current mode - IPR_IPLR = 0x110, // interrupt priority level register - IPR_INTID = 0x111, // interrupt ID register - IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register - IPR_IVPTBR = 0x113, // virtual page table base register - IPR_HWINT_CLR = 0x115, // H/W interrupt clear register - IPR_SL_XMIT = 0x116, // serial line transmit register - IPR_SL_RCV = 0x117, // serial line receive register - IPR_ICSR = 0x118, // instruction control and status register - IPR_IC_FLUSH = 0x119, // instruction cache flush control - IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register - IPR_PMCTR = 0x11c, // performance counter register - - // PAL temporary registers... - // register meanings gleaned from osfpal.s source code - IPR_PALtemp0 = 0x140, // local scratch - IPR_PALtemp1 = 0x141, // local scratch - IPR_PALtemp2 = 0x142, // entUna - IPR_PALtemp3 = 0x143, // CPU specific impure area pointer - IPR_PALtemp4 = 0x144, // memory management temp - IPR_PALtemp5 = 0x145, // memory management temp - IPR_PALtemp6 = 0x146, // memory management temp - IPR_PALtemp7 = 0x147, // entIF - IPR_PALtemp8 = 0x148, // intmask - IPR_PALtemp9 = 0x149, // entSys - IPR_PALtemp10 = 0x14a, // ?? - IPR_PALtemp11 = 0x14b, // entInt - IPR_PALtemp12 = 0x14c, // entArith - IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL - IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL - IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL - IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> - IPR_PALtemp17 = 0x151, // sysval - IPR_PALtemp18 = 0x152, // usp - IPR_PALtemp19 = 0x153, // ksp - IPR_PALtemp20 = 0x154, // PTBR - IPR_PALtemp21 = 0x155, // entMM - IPR_PALtemp22 = 0x156, // kgp - IPR_PALtemp23 = 0x157, // PCBB - - IPR_DTB_ASN = 0x200, // DTLB address space number register - IPR_DTB_CM = 0x201, // DTLB current mode register - IPR_DTB_TAG = 0x202, // DTLB tag register - IPR_DTB_PTE = 0x203, // DTLB page table entry register - IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register - - IPR_MM_STAT = 0x205, // data MMU fault status register - IPR_VA = 0x206, // fault virtual address register - IPR_VA_FORM = 0x207, // formatted virtual address register - IPR_MVPTBR = 0x208, // MTU virtual page table base register - IPR_DTB_IAP = 0x209, // DTLB invalidate all process register - IPR_DTB_IA = 0x20a, // DTLB invalidate all register - IPR_DTB_IS = 0x20b, // DTLB invalidate single register - IPR_ALT_MODE = 0x20c, // alternate mode register - IPR_CC = 0x20d, // cycle counter register - IPR_CC_CTL = 0x20e, // cycle counter control register - IPR_MCSR = 0x20f, // MTU control register - - IPR_DC_FLUSH = 0x210, - IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register - IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register - IPR_DC_TEST_TAG = 0x214, // Dcache test tag register - IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register - IPR_DC_MODE = 0x216, // Dcache mode register - IPR_MAF_MODE = 0x217, // miss address file mode register - - NumInternalProcRegs // number of IPR registers - }; -#else - const int NumInternalProcRegs = 0; -#endif - // Constants Related to the number of registers const int NumIntArchRegs = 32; diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index ea6fc67b2..31472ec0e 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -31,8 +31,9 @@ #ifndef __ARCH_ALPHA_REGFILE_HH__ #define __ARCH_ALPHA_REGFILE_HH__ -#include "arch/alpha/types.hh" #include "arch/alpha/isa_traits.hh" +#include "arch/alpha/ipr.hh" +#include "arch/alpha/types.hh" #include "sim/faults.hh" #include @@ -112,6 +113,11 @@ namespace AlphaISA int intr_flag; public: + MiscRegFile() + { + initializeIprTable(); + } + MiscReg readReg(int misc_reg); MiscReg readRegWithEffect(int misc_reg, Fault &fault, -- cgit v1.2.3 From 44f2c05118f46b996d13d7c3eac3227a8141e3fe Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 16:18:54 -0500 Subject: Forgot to change the index. --HG-- extra : convert_revision : 5a444e635d20bcca445a10e43592b6c10d25e879 --- src/arch/alpha/isa/decoder.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 852f483e0..0cbe38ceb 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -751,7 +751,7 @@ decode OPCODE default Unknown::unknown() { miscRegIndex <= MaxWriteOnlyIpr)) fault = new UnimplementedOpcodeFault; else - Ra = xc->readMiscRegWithEffect(ipr_index, fault); + Ra = xc->readMiscRegWithEffect(miscRegIndex, fault); }}, IsIprAccess); } } @@ -766,7 +766,7 @@ decode OPCODE default Unknown::unknown() { miscRegIndex <= MaxWriteOnlyIpr)) fault = new UnimplementedOpcodeFault; else - xc->setMiscRegWithEffect(ipr_index, Ra); + xc->setMiscRegWithEffect(miscRegIndex, Ra); if (traceData) { traceData->setData(Ra); } }}, IsIprAccess); } -- cgit v1.2.3 From ace4f0c188f3bbc921d003750dad1410877680d1 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 16:36:45 -0500 Subject: Made the old name refer to the miscreg index to prevent having to change code all over the place. --HG-- extra : convert_revision : e890a3ce420336acdb220396dcbf66d4b9974c76 --- src/arch/alpha/ev5.cc | 306 ++++++++++++++++++++++++------------------------- src/arch/alpha/ipr.cc | 148 ++++++++++++------------ src/arch/alpha/ipr.hh | 310 +++++++++++++++++++++++++------------------------- 3 files changed, 382 insertions(+), 382 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 56dadd6b1..7595423c3 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -62,7 +62,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId) AlphaFault *reset = new ResetFault; - tc->setPC(tc->readMiscReg(MISCREG_IPR_PAL_BASE) + reset->vect()); + tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect()); tc->setNextPC(tc->readPC() + sizeof(MachInst)); delete reset; @@ -79,9 +79,9 @@ AlphaISA::initIPRs(ThreadContext *tc, int cpuId) tc->setMiscReg(i, 0); } - tc->setMiscReg(MISCREG_IPR_PAL_BASE, PalBase); - tc->setMiscReg(MISCREG_IPR_MCSR, 0x6); - tc->setMiscReg(MISCREG_IPR_PALtemp16, cpuId); + tc->setMiscReg(IPR_PAL_BASE, PalBase); + tc->setMiscReg(IPR_MCSR, 0x6); + tc->setMiscReg(IPR_PALtemp16, cpuId); } @@ -96,13 +96,13 @@ AlphaISA::processInterrupts(CPU *cpu) cpu->checkInterrupts = false; - if (cpu->readMiscReg(MISCREG_IPR_ASTRR)) + if (cpu->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (cpu->readMiscReg(MISCREG_IPR_SIRR)) { + if (cpu->readMiscReg(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (cpu->readMiscReg(MISCREG_IPR_SIRR) & (ULL(1) << i)) { + if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of the 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -123,12 +123,12 @@ AlphaISA::processInterrupts(CPU *cpu) } } - if (ipl && ipl > cpu->readMiscReg(MISCREG_IPR_IPLR)) { - cpu->setMiscReg(MISCREG_IPR_ISR, summary); - cpu->setMiscReg(MISCREG_IPR_INTID, ipl); + if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { + cpu->setMiscReg(IPR_ISR, summary); + cpu->setMiscReg(IPR_INTID, ipl); cpu->trap(new InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - cpu->readMiscReg(MISCREG_IPR_IPLR), ipl, summary); + cpu->readMiscReg(IPR_IPLR), ipl, summary); } } @@ -150,7 +150,7 @@ SimpleThread::hwrei() if (!inPalMode()) return new UnimplementedOpcodeFault; - setNextPC(readMiscReg(AlphaISA::MISCREG_IPR_EXC_ADDR)); + setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); if (!misspeculating()) { if (kernelStats) @@ -166,13 +166,13 @@ SimpleThread::hwrei() int AlphaISA::MiscRegFile::getInstAsid() { - return EV5::ITB_ASN_ASN(ipr[MISCREG_IPR_ITB_ASN]); + return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } int AlphaISA::MiscRegFile::getDataAsid() { - return EV5::DTB_ASN_ASN(ipr[MISCREG_IPR_DTB_ASN]); + return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } AlphaISA::MiscReg @@ -181,71 +181,71 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) uint64_t retval = 0; // return value, default 0 switch (idx) { - case AlphaISA::MISCREG_IPR_PALtemp0: - case AlphaISA::MISCREG_IPR_PALtemp1: - case AlphaISA::MISCREG_IPR_PALtemp2: - case AlphaISA::MISCREG_IPR_PALtemp3: - case AlphaISA::MISCREG_IPR_PALtemp4: - case AlphaISA::MISCREG_IPR_PALtemp5: - case AlphaISA::MISCREG_IPR_PALtemp6: - case AlphaISA::MISCREG_IPR_PALtemp7: - case AlphaISA::MISCREG_IPR_PALtemp8: - case AlphaISA::MISCREG_IPR_PALtemp9: - case AlphaISA::MISCREG_IPR_PALtemp10: - case AlphaISA::MISCREG_IPR_PALtemp11: - case AlphaISA::MISCREG_IPR_PALtemp12: - case AlphaISA::MISCREG_IPR_PALtemp13: - case AlphaISA::MISCREG_IPR_PALtemp14: - case AlphaISA::MISCREG_IPR_PALtemp15: - case AlphaISA::MISCREG_IPR_PALtemp16: - case AlphaISA::MISCREG_IPR_PALtemp17: - case AlphaISA::MISCREG_IPR_PALtemp18: - case AlphaISA::MISCREG_IPR_PALtemp19: - case AlphaISA::MISCREG_IPR_PALtemp20: - case AlphaISA::MISCREG_IPR_PALtemp21: - case AlphaISA::MISCREG_IPR_PALtemp22: - case AlphaISA::MISCREG_IPR_PALtemp23: - case AlphaISA::MISCREG_IPR_PAL_BASE: - - case AlphaISA::MISCREG_IPR_IVPTBR: - case AlphaISA::MISCREG_IPR_DC_MODE: - case AlphaISA::MISCREG_IPR_MAF_MODE: - case AlphaISA::MISCREG_IPR_ISR: - case AlphaISA::MISCREG_IPR_EXC_ADDR: - case AlphaISA::MISCREG_IPR_IC_PERR_STAT: - case AlphaISA::MISCREG_IPR_DC_PERR_STAT: - case AlphaISA::MISCREG_IPR_MCSR: - case AlphaISA::MISCREG_IPR_ASTRR: - case AlphaISA::MISCREG_IPR_ASTER: - case AlphaISA::MISCREG_IPR_SIRR: - case AlphaISA::MISCREG_IPR_ICSR: - case AlphaISA::MISCREG_IPR_ICM: - case AlphaISA::MISCREG_IPR_DTB_CM: - case AlphaISA::MISCREG_IPR_IPLR: - case AlphaISA::MISCREG_IPR_INTID: - case AlphaISA::MISCREG_IPR_PMCTR: + case AlphaISA::IPR_PALtemp0: + case AlphaISA::IPR_PALtemp1: + case AlphaISA::IPR_PALtemp2: + case AlphaISA::IPR_PALtemp3: + case AlphaISA::IPR_PALtemp4: + case AlphaISA::IPR_PALtemp5: + case AlphaISA::IPR_PALtemp6: + case AlphaISA::IPR_PALtemp7: + case AlphaISA::IPR_PALtemp8: + case AlphaISA::IPR_PALtemp9: + case AlphaISA::IPR_PALtemp10: + case AlphaISA::IPR_PALtemp11: + case AlphaISA::IPR_PALtemp12: + case AlphaISA::IPR_PALtemp13: + case AlphaISA::IPR_PALtemp14: + case AlphaISA::IPR_PALtemp15: + case AlphaISA::IPR_PALtemp16: + case AlphaISA::IPR_PALtemp17: + case AlphaISA::IPR_PALtemp18: + case AlphaISA::IPR_PALtemp19: + case AlphaISA::IPR_PALtemp20: + case AlphaISA::IPR_PALtemp21: + case AlphaISA::IPR_PALtemp22: + case AlphaISA::IPR_PALtemp23: + case AlphaISA::IPR_PAL_BASE: + + case AlphaISA::IPR_IVPTBR: + case AlphaISA::IPR_DC_MODE: + case AlphaISA::IPR_MAF_MODE: + case AlphaISA::IPR_ISR: + case AlphaISA::IPR_EXC_ADDR: + case AlphaISA::IPR_IC_PERR_STAT: + case AlphaISA::IPR_DC_PERR_STAT: + case AlphaISA::IPR_MCSR: + case AlphaISA::IPR_ASTRR: + case AlphaISA::IPR_ASTER: + case AlphaISA::IPR_SIRR: + case AlphaISA::IPR_ICSR: + case AlphaISA::IPR_ICM: + case AlphaISA::IPR_DTB_CM: + case AlphaISA::IPR_IPLR: + case AlphaISA::IPR_INTID: + case AlphaISA::IPR_PMCTR: // no side-effect retval = ipr[idx]; break; - case AlphaISA::MISCREG_IPR_CC: + case AlphaISA::IPR_CC: retval |= ipr[idx] & ULL(0xffffffff00000000); retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); break; - case AlphaISA::MISCREG_IPR_VA: + case AlphaISA::IPR_VA: retval = ipr[idx]; break; - case AlphaISA::MISCREG_IPR_VA_FORM: - case AlphaISA::MISCREG_IPR_MM_STAT: - case AlphaISA::MISCREG_IPR_IFAULT_VA_FORM: - case AlphaISA::MISCREG_IPR_EXC_MASK: - case AlphaISA::MISCREG_IPR_EXC_SUM: + case AlphaISA::IPR_VA_FORM: + case AlphaISA::IPR_MM_STAT: + case AlphaISA::IPR_IFAULT_VA_FORM: + case AlphaISA::IPR_EXC_MASK: + case AlphaISA::IPR_EXC_SUM: retval = ipr[idx]; break; - case AlphaISA::MISCREG_IPR_DTB_PTE: + case AlphaISA::IPR_DTB_PTE: { AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); @@ -260,15 +260,15 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) break; // write only registers - case AlphaISA::MISCREG_IPR_HWINT_CLR: - case AlphaISA::MISCREG_IPR_SL_XMIT: - case AlphaISA::MISCREG_IPR_DC_FLUSH: - case AlphaISA::MISCREG_IPR_IC_FLUSH: - case AlphaISA::MISCREG_IPR_ALT_MODE: - case AlphaISA::MISCREG_IPR_DTB_IA: - case AlphaISA::MISCREG_IPR_DTB_IAP: - case AlphaISA::MISCREG_IPR_ITB_IA: - case AlphaISA::MISCREG_IPR_ITB_IAP: + case AlphaISA::IPR_HWINT_CLR: + case AlphaISA::IPR_SL_XMIT: + case AlphaISA::IPR_DC_FLUSH: + case AlphaISA::IPR_IC_FLUSH: + case AlphaISA::IPR_ALT_MODE: + case AlphaISA::IPR_DTB_IA: + case AlphaISA::IPR_DTB_IAP: + case AlphaISA::IPR_ITB_IA: + case AlphaISA::IPR_ITB_IAP: fault = new UnimplementedOpcodeFault; break; @@ -295,52 +295,52 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) return NoFault; switch (idx) { - case AlphaISA::MISCREG_IPR_PALtemp0: - case AlphaISA::MISCREG_IPR_PALtemp1: - case AlphaISA::MISCREG_IPR_PALtemp2: - case AlphaISA::MISCREG_IPR_PALtemp3: - case AlphaISA::MISCREG_IPR_PALtemp4: - case AlphaISA::MISCREG_IPR_PALtemp5: - case AlphaISA::MISCREG_IPR_PALtemp6: - case AlphaISA::MISCREG_IPR_PALtemp7: - case AlphaISA::MISCREG_IPR_PALtemp8: - case AlphaISA::MISCREG_IPR_PALtemp9: - case AlphaISA::MISCREG_IPR_PALtemp10: - case AlphaISA::MISCREG_IPR_PALtemp11: - case AlphaISA::MISCREG_IPR_PALtemp12: - case AlphaISA::MISCREG_IPR_PALtemp13: - case AlphaISA::MISCREG_IPR_PALtemp14: - case AlphaISA::MISCREG_IPR_PALtemp15: - case AlphaISA::MISCREG_IPR_PALtemp16: - case AlphaISA::MISCREG_IPR_PALtemp17: - case AlphaISA::MISCREG_IPR_PALtemp18: - case AlphaISA::MISCREG_IPR_PALtemp19: - case AlphaISA::MISCREG_IPR_PALtemp20: - case AlphaISA::MISCREG_IPR_PALtemp21: - case AlphaISA::MISCREG_IPR_PALtemp22: - case AlphaISA::MISCREG_IPR_PAL_BASE: - case AlphaISA::MISCREG_IPR_IC_PERR_STAT: - case AlphaISA::MISCREG_IPR_DC_PERR_STAT: - case AlphaISA::MISCREG_IPR_PMCTR: + case AlphaISA::IPR_PALtemp0: + case AlphaISA::IPR_PALtemp1: + case AlphaISA::IPR_PALtemp2: + case AlphaISA::IPR_PALtemp3: + case AlphaISA::IPR_PALtemp4: + case AlphaISA::IPR_PALtemp5: + case AlphaISA::IPR_PALtemp6: + case AlphaISA::IPR_PALtemp7: + case AlphaISA::IPR_PALtemp8: + case AlphaISA::IPR_PALtemp9: + case AlphaISA::IPR_PALtemp10: + case AlphaISA::IPR_PALtemp11: + case AlphaISA::IPR_PALtemp12: + case AlphaISA::IPR_PALtemp13: + case AlphaISA::IPR_PALtemp14: + case AlphaISA::IPR_PALtemp15: + case AlphaISA::IPR_PALtemp16: + case AlphaISA::IPR_PALtemp17: + case AlphaISA::IPR_PALtemp18: + case AlphaISA::IPR_PALtemp19: + case AlphaISA::IPR_PALtemp20: + case AlphaISA::IPR_PALtemp21: + case AlphaISA::IPR_PALtemp22: + case AlphaISA::IPR_PAL_BASE: + case AlphaISA::IPR_IC_PERR_STAT: + case AlphaISA::IPR_DC_PERR_STAT: + case AlphaISA::IPR_PMCTR: // write entire quad w/ no side-effect ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_CC_CTL: + case AlphaISA::IPR_CC_CTL: // This IPR resets the cycle counter. We assume this only // happens once... let's verify that. assert(ipr[idx] == 0); ipr[idx] = 1; break; - case AlphaISA::MISCREG_IPR_CC: + case AlphaISA::IPR_CC: // This IPR only writes the upper 64 bits. It's ok to write // all 64 here since we mask out the lower 32 in rpcc (see // isa_desc). ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_PALtemp23: + case AlphaISA::IPR_PALtemp23: // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; @@ -348,23 +348,23 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->context(old, val, tc); break; - case AlphaISA::MISCREG_IPR_DTB_PTE: + case AlphaISA::IPR_DTB_PTE: // write entire quad w/ no side-effect, tag is forthcoming ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_EXC_ADDR: + case AlphaISA::IPR_EXC_ADDR: // second least significant bit in PC is always zero ipr[idx] = val & ~2; break; - case AlphaISA::MISCREG_IPR_ASTRR: - case AlphaISA::MISCREG_IPR_ASTER: + case AlphaISA::IPR_ASTRR: + case AlphaISA::IPR_ASTER: // only write least significant four bits - privilege mask ipr[idx] = val & 0xf; break; - case AlphaISA::MISCREG_IPR_IPLR: + case AlphaISA::IPR_IPLR: #ifdef DEBUG if (break_ipl != -1 && break_ipl == (val & 0x1f)) debug_break(); @@ -376,7 +376,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->swpipl(ipr[idx]); break; - case AlphaISA::MISCREG_IPR_DTB_CM: + case AlphaISA::IPR_DTB_CM: if (val & 0x18) { if (tc->getKernelStats()) tc->getKernelStats()->mode(Kernel::user, tc); @@ -385,121 +385,121 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->mode(Kernel::kernel, tc); } - case AlphaISA::MISCREG_IPR_ICM: + case AlphaISA::IPR_ICM: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case AlphaISA::MISCREG_IPR_ALT_MODE: + case AlphaISA::IPR_ALT_MODE: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case AlphaISA::MISCREG_IPR_MCSR: + case AlphaISA::IPR_MCSR: // more here after optimization... ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_SIRR: + case AlphaISA::IPR_SIRR: // only write software interrupt mask ipr[idx] = val & 0x7fff0; break; - case AlphaISA::MISCREG_IPR_ICSR: + case AlphaISA::IPR_ICSR: ipr[idx] = val & ULL(0xffffff0300); break; - case AlphaISA::MISCREG_IPR_IVPTBR: - case AlphaISA::MISCREG_IPR_MVPTBR: + case AlphaISA::IPR_IVPTBR: + case AlphaISA::IPR_MVPTBR: ipr[idx] = val & ULL(0xffffffffc0000000); break; - case AlphaISA::MISCREG_IPR_DC_TEST_CTL: + case AlphaISA::IPR_DC_TEST_CTL: ipr[idx] = val & 0x1ffb; break; - case AlphaISA::MISCREG_IPR_DC_MODE: - case AlphaISA::MISCREG_IPR_MAF_MODE: + case AlphaISA::IPR_DC_MODE: + case AlphaISA::IPR_MAF_MODE: ipr[idx] = val & 0x3f; break; - case AlphaISA::MISCREG_IPR_ITB_ASN: + case AlphaISA::IPR_ITB_ASN: ipr[idx] = val & 0x7f0; break; - case AlphaISA::MISCREG_IPR_DTB_ASN: + case AlphaISA::IPR_DTB_ASN: ipr[idx] = val & ULL(0xfe00000000000000); break; - case AlphaISA::MISCREG_IPR_EXC_SUM: - case AlphaISA::MISCREG_IPR_EXC_MASK: + case AlphaISA::IPR_EXC_SUM: + case AlphaISA::IPR_EXC_MASK: // any write to this register clears it ipr[idx] = 0; break; - case AlphaISA::MISCREG_IPR_INTID: - case AlphaISA::MISCREG_IPR_SL_RCV: - case AlphaISA::MISCREG_IPR_MM_STAT: - case AlphaISA::MISCREG_IPR_ITB_PTE_TEMP: - case AlphaISA::MISCREG_IPR_DTB_PTE_TEMP: + case AlphaISA::IPR_INTID: + case AlphaISA::IPR_SL_RCV: + case AlphaISA::IPR_MM_STAT: + case AlphaISA::IPR_ITB_PTE_TEMP: + case AlphaISA::IPR_DTB_PTE_TEMP: // read-only registers return new UnimplementedOpcodeFault; - case AlphaISA::MISCREG_IPR_HWINT_CLR: - case AlphaISA::MISCREG_IPR_SL_XMIT: - case AlphaISA::MISCREG_IPR_DC_FLUSH: - case AlphaISA::MISCREG_IPR_IC_FLUSH: + case AlphaISA::IPR_HWINT_CLR: + case AlphaISA::IPR_SL_XMIT: + case AlphaISA::IPR_DC_FLUSH: + case AlphaISA::IPR_IC_FLUSH: // the following are write only ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_DTB_IA: + case AlphaISA::IPR_DTB_IA: // really a control write ipr[idx] = 0; tc->getDTBPtr()->flushAll(); break; - case AlphaISA::MISCREG_IPR_DTB_IAP: + case AlphaISA::IPR_DTB_IAP: // really a control write ipr[idx] = 0; tc->getDTBPtr()->flushProcesses(); break; - case AlphaISA::MISCREG_IPR_DTB_IS: + case AlphaISA::IPR_DTB_IS: // really a control write ipr[idx] = val; tc->getDTBPtr()->flushAddr(val, - DTB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_DTB_ASN])); + DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); break; - case AlphaISA::MISCREG_IPR_DTB_TAG: { + case AlphaISA::IPR_DTB_TAG: { struct AlphaISA::PTE pte; // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]) != 0) + if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) panic("PTE GH field != 0"); // write entire quad ipr[idx] = val; // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_DTB_ASN]); + pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); + pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); + pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); + pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); + pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); + pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); + pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); // insert new TAG/PTE value into data TLB tc->getDTBPtr()->insert(val, pte); } break; - case AlphaISA::MISCREG_IPR_ITB_PTE: { + case AlphaISA::IPR_ITB_PTE: { struct AlphaISA::PTE pte; // FIXME: granularity hints NYI... @@ -516,33 +516,33 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) pte.fonr = ITB_PTE_FONR(val); pte.fonw = ITB_PTE_FONW(val); pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_ITB_ASN]); + pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); // insert new TAG/PTE value into data TLB - tc->getITBPtr()->insert(ipr[AlphaISA::MISCREG_IPR_ITB_TAG], pte); + tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); } break; - case AlphaISA::MISCREG_IPR_ITB_IA: + case AlphaISA::IPR_ITB_IA: // really a control write ipr[idx] = 0; tc->getITBPtr()->flushAll(); break; - case AlphaISA::MISCREG_IPR_ITB_IAP: + case AlphaISA::IPR_ITB_IAP: // really a control write ipr[idx] = 0; tc->getITBPtr()->flushProcesses(); break; - case AlphaISA::MISCREG_IPR_ITB_IS: + case AlphaISA::IPR_ITB_IS: // really a control write ipr[idx] = val; tc->getITBPtr()->flushAddr(val, - ITB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_ITB_ASN])); + ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); break; default: diff --git a/src/arch/alpha/ipr.cc b/src/arch/alpha/ipr.cc index 50086a845..8e83102eb 100644 --- a/src/arch/alpha/ipr.cc +++ b/src/arch/alpha/ipr.cc @@ -38,89 +38,89 @@ namespace AlphaISA md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = { //Write only - IPR_HWINT_CLR, // H/W interrupt clear register - IPR_SL_XMIT, // serial line transmit register - IPR_DC_FLUSH, - IPR_IC_FLUSH, // instruction cache flush control - IPR_ALT_MODE, // alternate mode register - IPR_DTB_IA, // DTLB invalidate all register - IPR_DTB_IAP, // DTLB invalidate all process register - IPR_ITB_IA, // ITLB invalidate all register - IPR_ITB_IAP, // ITLB invalidate all process register + RAW_IPR_HWINT_CLR, // H/W interrupt clear register + RAW_IPR_SL_XMIT, // serial line transmit register + RAW_IPR_DC_FLUSH, + RAW_IPR_IC_FLUSH, // instruction cache flush control + RAW_IPR_ALT_MODE, // alternate mode register + RAW_IPR_DTB_IA, // DTLB invalidate all register + RAW_IPR_DTB_IAP, // DTLB invalidate all process register + RAW_IPR_ITB_IA, // ITLB invalidate all register + RAW_IPR_ITB_IAP, // ITLB invalidate all process register //Read only - IPR_INTID, // interrupt ID register - IPR_SL_RCV, // serial line receive register - IPR_MM_STAT, // data MMU fault status register - IPR_ITB_PTE_TEMP, // ITLB page table entry temp register - IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register + RAW_IPR_INTID, // interrupt ID register + RAW_IPR_SL_RCV, // serial line receive register + RAW_IPR_MM_STAT, // data MMU fault status register + RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register + RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register - IPR_ISR, // interrupt summary register - IPR_ITB_TAG, // ITLB tag register - IPR_ITB_PTE, // ITLB page table entry register - IPR_ITB_ASN, // ITLB address space register - IPR_ITB_IS, // ITLB invalidate select register - IPR_SIRR, // software interrupt request register - IPR_ASTRR, // asynchronous system trap request register - IPR_ASTER, // asynchronous system trap enable register - IPR_EXC_ADDR, // exception address register - IPR_EXC_SUM, // exception summary register - IPR_EXC_MASK, // exception mask register - IPR_PAL_BASE, // PAL base address register - IPR_ICM, // instruction current mode - IPR_IPLR, // interrupt priority level register - IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register - IPR_IVPTBR, // virtual page table base register - IPR_ICSR, // instruction control and status register - IPR_IC_PERR_STAT, // inst cache parity error status register - IPR_PMCTR, // performance counter register + RAW_IPR_ISR, // interrupt summary register + RAW_IPR_ITB_TAG, // ITLB tag register + RAW_IPR_ITB_PTE, // ITLB page table entry register + RAW_IPR_ITB_ASN, // ITLB address space register + RAW_IPR_ITB_IS, // ITLB invalidate select register + RAW_IPR_SIRR, // software interrupt request register + RAW_IPR_ASTRR, // asynchronous system trap request register + RAW_IPR_ASTER, // asynchronous system trap enable register + RAW_IPR_EXC_ADDR, // exception address register + RAW_IPR_EXC_SUM, // exception summary register + RAW_IPR_EXC_MASK, // exception mask register + RAW_IPR_PAL_BASE, // PAL base address register + RAW_IPR_ICM, // instruction current mode + RAW_IPR_IPLR, // interrupt priority level register + RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register + RAW_IPR_IVPTBR, // virtual page table base register + RAW_IPR_ICSR, // instruction control and status register + RAW_IPR_IC_PERR_STAT, // inst cache parity error status register + RAW_IPR_PMCTR, // performance counter register // PAL temporary registers... // register meanings gleaned from osfpal.s source code - IPR_PALtemp0, // local scratch - IPR_PALtemp1, // local scratch - IPR_PALtemp2, // entUna - IPR_PALtemp3, // CPU specific impure area pointer - IPR_PALtemp4, // memory management temp - IPR_PALtemp5, // memory management temp - IPR_PALtemp6, // memory management temp - IPR_PALtemp7, // entIF - IPR_PALtemp8, // intmask - IPR_PALtemp9, // entSys - IPR_PALtemp10, // ?? - IPR_PALtemp11, // entInt - IPR_PALtemp12, // entArith - IPR_PALtemp13, // reserved for platform specific PAL - IPR_PALtemp14, // reserved for platform specific PAL - IPR_PALtemp15, // reserved for platform specific PAL - IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> - IPR_PALtemp17, // sysval - IPR_PALtemp18, // usp - IPR_PALtemp19, // ksp - IPR_PALtemp20, // PTBR - IPR_PALtemp21, // entMM - IPR_PALtemp22, // kgp - IPR_PALtemp23, // PCBB + RAW_IPR_PALtemp0, // local scratch + RAW_IPR_PALtemp1, // local scratch + RAW_IPR_PALtemp2, // entUna + RAW_IPR_PALtemp3, // CPU specific impure area pointer + RAW_IPR_PALtemp4, // memory management temp + RAW_IPR_PALtemp5, // memory management temp + RAW_IPR_PALtemp6, // memory management temp + RAW_IPR_PALtemp7, // entIF + RAW_IPR_PALtemp8, // intmask + RAW_IPR_PALtemp9, // entSys + RAW_IPR_PALtemp10, // ?? + RAW_IPR_PALtemp11, // entInt + RAW_IPR_PALtemp12, // entArith + RAW_IPR_PALtemp13, // reserved for platform specific PAL + RAW_IPR_PALtemp14, // reserved for platform specific PAL + RAW_IPR_PALtemp15, // reserved for platform specific PAL + RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> + RAW_IPR_PALtemp17, // sysval + RAW_IPR_PALtemp18, // usp + RAW_IPR_PALtemp19, // ksp + RAW_IPR_PALtemp20, // PTBR + RAW_IPR_PALtemp21, // entMM + RAW_IPR_PALtemp22, // kgp + RAW_IPR_PALtemp23, // PCBB - IPR_DTB_ASN, // DTLB address space number register - IPR_DTB_CM, // DTLB current mode register - IPR_DTB_TAG, // DTLB tag register - IPR_DTB_PTE, // DTLB page table entry register + RAW_IPR_DTB_ASN, // DTLB address space number register + RAW_IPR_DTB_CM, // DTLB current mode register + RAW_IPR_DTB_TAG, // DTLB tag register + RAW_IPR_DTB_PTE, // DTLB page table entry register - IPR_VA, // fault virtual address register - IPR_VA_FORM, // formatted virtual address register - IPR_MVPTBR, // MTU virtual page table base register - IPR_DTB_IS, // DTLB invalidate single register - IPR_CC, // cycle counter register - IPR_CC_CTL, // cycle counter control register - IPR_MCSR, // MTU control register + RAW_IPR_VA, // fault virtual address register + RAW_IPR_VA_FORM, // formatted virtual address register + RAW_IPR_MVPTBR, // MTU virtual page table base register + RAW_IPR_DTB_IS, // DTLB invalidate single register + RAW_IPR_CC, // cycle counter register + RAW_IPR_CC_CTL, // cycle counter control register + RAW_IPR_MCSR, // MTU control register - IPR_DC_PERR_STAT, // Dcache parity error status register - IPR_DC_TEST_CTL, // Dcache test tag control register - IPR_DC_TEST_TAG, // Dcache test tag register - IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register - IPR_DC_MODE, // Dcache mode register - IPR_MAF_MODE // miss address file mode register + RAW_IPR_DC_PERR_STAT, // Dcache parity error status register + RAW_IPR_DC_TEST_CTL, // Dcache test tag control register + RAW_IPR_DC_TEST_TAG, // Dcache test tag register + RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register + RAW_IPR_DC_MODE, // Dcache mode register + RAW_IPR_MAF_MODE // miss address file mode register }; int IprToMiscRegIndex[MaxInternalProcRegs]; diff --git a/src/arch/alpha/ipr.hh b/src/arch/alpha/ipr.hh index dba0733ba..17518c0fe 100644 --- a/src/arch/alpha/ipr.hh +++ b/src/arch/alpha/ipr.hh @@ -40,86 +40,86 @@ namespace AlphaISA // enum md_ipr_names { - IPR_ISR = 0x100, // interrupt summary register - IPR_ITB_TAG = 0x101, // ITLB tag register - IPR_ITB_PTE = 0x102, // ITLB page table entry register - IPR_ITB_ASN = 0x103, // ITLB address space register - IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register - IPR_ITB_IA = 0x105, // ITLB invalidate all register - IPR_ITB_IAP = 0x106, // ITLB invalidate all process register - IPR_ITB_IS = 0x107, // ITLB invalidate select register - IPR_SIRR = 0x108, // software interrupt request register - IPR_ASTRR = 0x109, // asynchronous system trap request register - IPR_ASTER = 0x10a, // asynchronous system trap enable register - IPR_EXC_ADDR = 0x10b, // exception address register - IPR_EXC_SUM = 0x10c, // exception summary register - IPR_EXC_MASK = 0x10d, // exception mask register - IPR_PAL_BASE = 0x10e, // PAL base address register - IPR_ICM = 0x10f, // instruction current mode - IPR_IPLR = 0x110, // interrupt priority level register - IPR_INTID = 0x111, // interrupt ID register - IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register - IPR_IVPTBR = 0x113, // virtual page table base register - IPR_HWINT_CLR = 0x115, // H/W interrupt clear register - IPR_SL_XMIT = 0x116, // serial line transmit register - IPR_SL_RCV = 0x117, // serial line receive register - IPR_ICSR = 0x118, // instruction control and status register - IPR_IC_FLUSH = 0x119, // instruction cache flush control - IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register - IPR_PMCTR = 0x11c, // performance counter register + RAW_IPR_ISR = 0x100, // interrupt summary register + RAW_IPR_ITB_TAG = 0x101, // ITLB tag register + RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry register + RAW_IPR_ITB_ASN = 0x103, // ITLB address space register + RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register + RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all register + RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process register + RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select register + RAW_IPR_SIRR = 0x108, // software interrupt request register + RAW_IPR_ASTRR = 0x109, // asynchronous system trap request register + RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable register + RAW_IPR_EXC_ADDR = 0x10b, // exception address register + RAW_IPR_EXC_SUM = 0x10c, // exception summary register + RAW_IPR_EXC_MASK = 0x10d, // exception mask register + RAW_IPR_PAL_BASE = 0x10e, // PAL base address register + RAW_IPR_ICM = 0x10f, // instruction current mode + RAW_IPR_IPLR = 0x110, // interrupt priority level register + RAW_IPR_INTID = 0x111, // interrupt ID register + RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register + RAW_IPR_IVPTBR = 0x113, // virtual page table base register + RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear register + RAW_IPR_SL_XMIT = 0x116, // serial line transmit register + RAW_IPR_SL_RCV = 0x117, // serial line receive register + RAW_IPR_ICSR = 0x118, // instruction control and status register + RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control + RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register + RAW_IPR_PMCTR = 0x11c, // performance counter register // PAL temporary registers... // register meanings gleaned from osfpal.s source code - IPR_PALtemp0 = 0x140, // local scratch - IPR_PALtemp1 = 0x141, // local scratch - IPR_PALtemp2 = 0x142, // entUna - IPR_PALtemp3 = 0x143, // CPU specific impure area pointer - IPR_PALtemp4 = 0x144, // memory management temp - IPR_PALtemp5 = 0x145, // memory management temp - IPR_PALtemp6 = 0x146, // memory management temp - IPR_PALtemp7 = 0x147, // entIF - IPR_PALtemp8 = 0x148, // intmask - IPR_PALtemp9 = 0x149, // entSys - IPR_PALtemp10 = 0x14a, // ?? - IPR_PALtemp11 = 0x14b, // entInt - IPR_PALtemp12 = 0x14c, // entArith - IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL - IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL - IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL - IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> - IPR_PALtemp17 = 0x151, // sysval - IPR_PALtemp18 = 0x152, // usp - IPR_PALtemp19 = 0x153, // ksp - IPR_PALtemp20 = 0x154, // PTBR - IPR_PALtemp21 = 0x155, // entMM - IPR_PALtemp22 = 0x156, // kgp - IPR_PALtemp23 = 0x157, // PCBB - - IPR_DTB_ASN = 0x200, // DTLB address space number register - IPR_DTB_CM = 0x201, // DTLB current mode register - IPR_DTB_TAG = 0x202, // DTLB tag register - IPR_DTB_PTE = 0x203, // DTLB page table entry register - IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register - - IPR_MM_STAT = 0x205, // data MMU fault status register - IPR_VA = 0x206, // fault virtual address register - IPR_VA_FORM = 0x207, // formatted virtual address register - IPR_MVPTBR = 0x208, // MTU virtual page table base register - IPR_DTB_IAP = 0x209, // DTLB invalidate all process register - IPR_DTB_IA = 0x20a, // DTLB invalidate all register - IPR_DTB_IS = 0x20b, // DTLB invalidate single register - IPR_ALT_MODE = 0x20c, // alternate mode register - IPR_CC = 0x20d, // cycle counter register - IPR_CC_CTL = 0x20e, // cycle counter control register - IPR_MCSR = 0x20f, // MTU control register - - IPR_DC_FLUSH = 0x210, - IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register - IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register - IPR_DC_TEST_TAG = 0x214, // Dcache test tag register - IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register - IPR_DC_MODE = 0x216, // Dcache mode register - IPR_MAF_MODE = 0x217, // miss address file mode register + RAW_IPR_PALtemp0 = 0x140, // local scratch + RAW_IPR_PALtemp1 = 0x141, // local scratch + RAW_IPR_PALtemp2 = 0x142, // entUna + RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer + RAW_IPR_PALtemp4 = 0x144, // memory management temp + RAW_IPR_PALtemp5 = 0x145, // memory management temp + RAW_IPR_PALtemp6 = 0x146, // memory management temp + RAW_IPR_PALtemp7 = 0x147, // entIF + RAW_IPR_PALtemp8 = 0x148, // intmask + RAW_IPR_PALtemp9 = 0x149, // entSys + RAW_IPR_PALtemp10 = 0x14a, // ?? + RAW_IPR_PALtemp11 = 0x14b, // entInt + RAW_IPR_PALtemp12 = 0x14c, // entArith + RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL + RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL + RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL + RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> + RAW_IPR_PALtemp17 = 0x151, // sysval + RAW_IPR_PALtemp18 = 0x152, // usp + RAW_IPR_PALtemp19 = 0x153, // ksp + RAW_IPR_PALtemp20 = 0x154, // PTBR + RAW_IPR_PALtemp21 = 0x155, // entMM + RAW_IPR_PALtemp22 = 0x156, // kgp + RAW_IPR_PALtemp23 = 0x157, // PCBB + + RAW_IPR_DTB_ASN = 0x200, // DTLB address space number register + RAW_IPR_DTB_CM = 0x201, // DTLB current mode register + RAW_IPR_DTB_TAG = 0x202, // DTLB tag register + RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry register + RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register + + RAW_IPR_MM_STAT = 0x205, // data MMU fault status register + RAW_IPR_VA = 0x206, // fault virtual address register + RAW_IPR_VA_FORM = 0x207, // formatted virtual address register + RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base register + RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process register + RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all register + RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single register + RAW_IPR_ALT_MODE = 0x20c, // alternate mode register + RAW_IPR_CC = 0x20d, // cycle counter register + RAW_IPR_CC_CTL = 0x20e, // cycle counter control register + RAW_IPR_MCSR = 0x20f, // MTU control register + + RAW_IPR_DC_FLUSH = 0x210, + RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register + RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register + RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag register + RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register + RAW_IPR_DC_MODE = 0x216, // Dcache mode register + RAW_IPR_MAF_MODE = 0x217, // miss address file mode register MaxInternalProcRegs // number of IPR registers }; @@ -128,92 +128,92 @@ namespace AlphaISA { //Write only MinWriteOnlyIpr, - MISCREG_IPR_HWINT_CLR = MinWriteOnlyIpr, - MISCREG_IPR_SL_XMIT, - MISCREG_IPR_DC_FLUSH, - MISCREG_IPR_IC_FLUSH, - MISCREG_IPR_ALT_MODE, - MISCREG_IPR_DTB_IA, - MISCREG_IPR_DTB_IAP, - MISCREG_IPR_ITB_IA, + IPR_HWINT_CLR = MinWriteOnlyIpr, + IPR_SL_XMIT, + IPR_DC_FLUSH, + IPR_IC_FLUSH, + IPR_ALT_MODE, + IPR_DTB_IA, + IPR_DTB_IAP, + IPR_ITB_IA, MaxWriteOnlyIpr, - MISCREG_IPR_ITB_IAP = MaxWriteOnlyIpr, + IPR_ITB_IAP = MaxWriteOnlyIpr, //Read only MinReadOnlyIpr, - MISCREG_IPR_INTID = MinReadOnlyIpr, - MISCREG_IPR_SL_RCV, - MISCREG_IPR_MM_STAT, - MISCREG_IPR_ITB_PTE_TEMP, + IPR_INTID = MinReadOnlyIpr, + IPR_SL_RCV, + IPR_MM_STAT, + IPR_ITB_PTE_TEMP, MaxReadOnlyIpr, - MISCREG_IPR_DTB_PTE_TEMP = MaxReadOnlyIpr, - - MISCREG_IPR_ISR, - MISCREG_IPR_ITB_TAG, - MISCREG_IPR_ITB_PTE, - MISCREG_IPR_ITB_ASN, - MISCREG_IPR_ITB_IS, - MISCREG_IPR_SIRR, - MISCREG_IPR_ASTRR, - MISCREG_IPR_ASTER, - MISCREG_IPR_EXC_ADDR, - MISCREG_IPR_EXC_SUM, - MISCREG_IPR_EXC_MASK, - MISCREG_IPR_PAL_BASE, - MISCREG_IPR_ICM, - MISCREG_IPR_IPLR, - MISCREG_IPR_IFAULT_VA_FORM, - MISCREG_IPR_IVPTBR, - MISCREG_IPR_ICSR, - MISCREG_IPR_IC_PERR_STAT, - MISCREG_IPR_PMCTR, + IPR_DTB_PTE_TEMP = MaxReadOnlyIpr, + + IPR_ISR, + IPR_ITB_TAG, + IPR_ITB_PTE, + IPR_ITB_ASN, + IPR_ITB_IS, + IPR_SIRR, + IPR_ASTRR, + IPR_ASTER, + IPR_EXC_ADDR, + IPR_EXC_SUM, + IPR_EXC_MASK, + IPR_PAL_BASE, + IPR_ICM, + IPR_IPLR, + IPR_IFAULT_VA_FORM, + IPR_IVPTBR, + IPR_ICSR, + IPR_IC_PERR_STAT, + IPR_PMCTR, // PAL temporary registers... // register meanings gleaned from osfpal.s source code - MISCREG_IPR_PALtemp0, - MISCREG_IPR_PALtemp1, - MISCREG_IPR_PALtemp2, - MISCREG_IPR_PALtemp3, - MISCREG_IPR_PALtemp4, - MISCREG_IPR_PALtemp5, - MISCREG_IPR_PALtemp6, - MISCREG_IPR_PALtemp7, - MISCREG_IPR_PALtemp8, - MISCREG_IPR_PALtemp9, - MISCREG_IPR_PALtemp10, - MISCREG_IPR_PALtemp11, - MISCREG_IPR_PALtemp12, - MISCREG_IPR_PALtemp13, - MISCREG_IPR_PALtemp14, - MISCREG_IPR_PALtemp15, - MISCREG_IPR_PALtemp16, - MISCREG_IPR_PALtemp17, - MISCREG_IPR_PALtemp18, - MISCREG_IPR_PALtemp19, - MISCREG_IPR_PALtemp20, - MISCREG_IPR_PALtemp21, - MISCREG_IPR_PALtemp22, - MISCREG_IPR_PALtemp23, - - MISCREG_IPR_DTB_ASN, - MISCREG_IPR_DTB_CM, - MISCREG_IPR_DTB_TAG, - MISCREG_IPR_DTB_PTE, - - MISCREG_IPR_VA, - MISCREG_IPR_VA_FORM, - MISCREG_IPR_MVPTBR, - MISCREG_IPR_DTB_IS, - MISCREG_IPR_CC, - MISCREG_IPR_CC_CTL, - MISCREG_IPR_MCSR, - - MISCREG_IPR_DC_PERR_STAT, - MISCREG_IPR_DC_TEST_CTL, - MISCREG_IPR_DC_TEST_TAG, - MISCREG_IPR_DC_TEST_TAG_TEMP, - MISCREG_IPR_DC_MODE, - MISCREG_IPR_MAF_MODE, + IPR_PALtemp0, + IPR_PALtemp1, + IPR_PALtemp2, + IPR_PALtemp3, + IPR_PALtemp4, + IPR_PALtemp5, + IPR_PALtemp6, + IPR_PALtemp7, + IPR_PALtemp8, + IPR_PALtemp9, + IPR_PALtemp10, + IPR_PALtemp11, + IPR_PALtemp12, + IPR_PALtemp13, + IPR_PALtemp14, + IPR_PALtemp15, + IPR_PALtemp16, + IPR_PALtemp17, + IPR_PALtemp18, + IPR_PALtemp19, + IPR_PALtemp20, + IPR_PALtemp21, + IPR_PALtemp22, + IPR_PALtemp23, + + IPR_DTB_ASN, + IPR_DTB_CM, + IPR_DTB_TAG, + IPR_DTB_PTE, + + IPR_VA, + IPR_VA_FORM, + IPR_MVPTBR, + IPR_DTB_IS, + IPR_CC, + IPR_CC_CTL, + IPR_MCSR, + + IPR_DC_PERR_STAT, + IPR_DC_TEST_CTL, + IPR_DC_TEST_TAG, + IPR_DC_TEST_TAG_TEMP, + IPR_DC_MODE, + IPR_MAF_MODE, NumInternalProcRegs // number of IPR registers }; -- cgit v1.2.3 From ad201172c957665b65222aae45b2b19f3ac53fab Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 16:59:41 -0500 Subject: We don't include ipr.cc in SE builds, so don't call it. --HG-- extra : convert_revision : 45e52d7afbf74e0ddde11f58aeb084186389fc06 --- src/arch/alpha/regfile.hh | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/arch') diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 31472ec0e..8980fcb40 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -115,7 +115,9 @@ namespace AlphaISA public: MiscRegFile() { +#if FULL_SYSTEM initializeIprTable(); +#endif } MiscReg readReg(int misc_reg); -- cgit v1.2.3 From fb5ba85abbf3791498faab3328a73b3725dfc839 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 17:50:57 -0500 Subject: Make two simple utility functions to determine if a MiscReg index corresponding to an IPR is readable or writable. --HG-- extra : convert_revision : 89eebba5eec01e629213997d24c734a6acad0ecb --- src/arch/alpha/ipr.hh | 9 +++++++++ src/arch/alpha/isa/decoder.isa | 8 ++------ 2 files changed, 11 insertions(+), 6 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/ipr.hh b/src/arch/alpha/ipr.hh index 17518c0fe..51c1489b8 100644 --- a/src/arch/alpha/ipr.hh +++ b/src/arch/alpha/ipr.hh @@ -218,6 +218,15 @@ namespace AlphaISA NumInternalProcRegs // number of IPR registers }; + inline bool IprIsWritable(int index) + { + return index < minReadOnlyIpr || index > maxReadOnlyIpr; + } + + inline bool IprIsReadable(int index) + { + return index < minWriteOnlyIpr || index > maxWriteOnlyIpr; + } extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs]; extern int IprToMiscRegIndex[MaxInternalProcRegs]; diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 0cbe38ceb..550aa62a3 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -746,9 +746,7 @@ decode OPCODE default Unknown::unknown() { format HwMoveIPR { 1: hw_mfpr({{ int miscRegIndex = IprToMiscRegIndex[ipr_index]; - if(miscRegIndex < 0 || - (miscRegIndex >= MinWriteOnlyIpr && - miscRegIndex <= MaxWriteOnlyIpr)) + if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex)) fault = new UnimplementedOpcodeFault; else Ra = xc->readMiscRegWithEffect(miscRegIndex, fault); @@ -761,9 +759,7 @@ decode OPCODE default Unknown::unknown() { format HwMoveIPR { 1: hw_mtpr({{ int miscRegIndex = IprToMiscRegIndex[ipr_index]; - if(miscRegIndex < 0 || - (miscRegIndex >= MinReadOnlyIpr && - miscRegIndex <= MaxWriteOnlyIpr)) + if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex)) fault = new UnimplementedOpcodeFault; else xc->setMiscRegWithEffect(miscRegIndex, Ra); -- cgit v1.2.3 From 45368c03001690aa7ea697afdbfaca01477fbdb2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 18:01:31 -0500 Subject: Fix stupid typo --HG-- extra : convert_revision : fbfc82974e89b2c726b689674c9f5d957682b280 --- src/arch/alpha/ipr.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/ipr.hh b/src/arch/alpha/ipr.hh index 51c1489b8..b55154764 100644 --- a/src/arch/alpha/ipr.hh +++ b/src/arch/alpha/ipr.hh @@ -220,12 +220,12 @@ namespace AlphaISA inline bool IprIsWritable(int index) { - return index < minReadOnlyIpr || index > maxReadOnlyIpr; + return index < MinReadOnlyIpr || index > MaxReadOnlyIpr; } inline bool IprIsReadable(int index) { - return index < minWriteOnlyIpr || index > maxWriteOnlyIpr; + return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr; } extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs]; -- cgit v1.2.3 From 39de635fbfa281c2fa70b65833825e2559d029b9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 18:19:45 -0500 Subject: Check for out of range IPR values as well. --HG-- extra : convert_revision : 9ca241bb71d8a1d022e54485383a88d2abece663 --- src/arch/alpha/isa/decoder.isa | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 550aa62a3..e4cf96767 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -745,8 +745,10 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mfpr(); format HwMoveIPR { 1: hw_mfpr({{ - int miscRegIndex = IprToMiscRegIndex[ipr_index]; - if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex)) + miscRegIndex >= NumInternalProcRegs) + int miscRegIndex = (ipr_index < NumInternalProcRegs) ? + IprToMiscRegIndex[ipr_index] : -1; + if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || fault = new UnimplementedOpcodeFault; else Ra = xc->readMiscRegWithEffect(miscRegIndex, fault); @@ -758,7 +760,8 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mtpr(); format HwMoveIPR { 1: hw_mtpr({{ - int miscRegIndex = IprToMiscRegIndex[ipr_index]; + int miscRegIndex = (ipr_index < NumInternalProcRegs) ? + IprToMiscRegIndex[ipr_index] : -1; if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex)) fault = new UnimplementedOpcodeFault; else -- cgit v1.2.3 From 1dd903e856e2e9995a85ac79e6519ff2d1f4d790 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 18:39:17 -0500 Subject: Fix another typo --HG-- extra : convert_revision : ad7058babf2a13bfe543e05f2662dc49a18a8b8b --- src/arch/alpha/isa/decoder.isa | 1 - 1 file changed, 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index e4cf96767..c5f47aaa2 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -745,7 +745,6 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mfpr(); format HwMoveIPR { 1: hw_mfpr({{ - miscRegIndex >= NumInternalProcRegs) int miscRegIndex = (ipr_index < NumInternalProcRegs) ? IprToMiscRegIndex[ipr_index] : -1; if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || -- cgit v1.2.3 From 1543c3d0a11d77ac82658fdace755a0967d32cbb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 18:51:26 -0500 Subject: More typos! I need to get nfs to work. --HG-- extra : convert_revision : f5693e96d376254f777fb0cce7b5be3d36efbea9 --- src/arch/alpha/isa/decoder.isa | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index c5f47aaa2..584d64a3d 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -748,6 +748,7 @@ decode OPCODE default Unknown::unknown() { int miscRegIndex = (ipr_index < NumInternalProcRegs) ? IprToMiscRegIndex[ipr_index] : -1; if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || + miscRegIndex >= NumInternalProcRegs) fault = new UnimplementedOpcodeFault; else Ra = xc->readMiscRegWithEffect(miscRegIndex, fault); @@ -761,7 +762,8 @@ decode OPCODE default Unknown::unknown() { 1: hw_mtpr({{ int miscRegIndex = (ipr_index < NumInternalProcRegs) ? IprToMiscRegIndex[ipr_index] : -1; - if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex)) + if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) + miscRegIndex >= NumInternalProcRegs) fault = new UnimplementedOpcodeFault; else xc->setMiscRegWithEffect(miscRegIndex, Ra); -- cgit v1.2.3 From f3ba6d20f6070c30418866e627e2418f39b433dd Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 18:59:50 -0500 Subject: Arg! --HG-- extra : convert_revision : 8328d002780c0291e7eb264076a62084de88b7a5 --- src/arch/alpha/isa/decoder.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 584d64a3d..f5483d9c0 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -762,7 +762,7 @@ decode OPCODE default Unknown::unknown() { 1: hw_mtpr({{ int miscRegIndex = (ipr_index < NumInternalProcRegs) ? IprToMiscRegIndex[ipr_index] : -1; - if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) + if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || miscRegIndex >= NumInternalProcRegs) fault = new UnimplementedOpcodeFault; else -- cgit v1.2.3 From 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Nov 2006 16:44:45 -0500 Subject: Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675 --- src/arch/alpha/ev5.cc | 17 +++++----- src/arch/alpha/isa/decoder.isa | 8 ++--- src/arch/alpha/isa/fp.isa | 2 +- src/arch/alpha/regfile.hh | 43 +++++++++++------------- src/arch/mips/regfile/misc_regfile.hh | 10 +++--- src/arch/mips/regfile/regfile.hh | 34 +++++++++---------- src/arch/sparc/isa/decoder.isa | 6 ++-- src/arch/sparc/miscregfile.cc | 62 ++++++++++++++++++++++++----------- src/arch/sparc/miscregfile.hh | 16 +++++++++ src/arch/sparc/regfile.cc | 31 ++++++++---------- src/arch/sparc/regfile.hh | 28 ++++++++++------ src/arch/sparc/tlb.hh | 28 ++++++++++++++++ 12 files changed, 174 insertions(+), 111 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 7595423c3..314b445e0 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -60,7 +60,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId) tc->setIntReg(16, cpuId); tc->setIntReg(0, cpuId); - AlphaFault *reset = new ResetFault; + AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault; tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect()); tc->setNextPC(tc->readPC() + sizeof(MachInst)); @@ -176,7 +176,7 @@ AlphaISA::MiscRegFile::getDataAsid() } AlphaISA::MiscReg -AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) +AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc) { uint64_t retval = 0; // return value, default 0 @@ -269,12 +269,12 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) case AlphaISA::IPR_DTB_IAP: case AlphaISA::IPR_ITB_IA: case AlphaISA::IPR_ITB_IAP: - fault = new UnimplementedOpcodeFault; + panic("Tried to read write only register %d\n", idx); break; default: // invalid IPR - fault = new UnimplementedOpcodeFault; + panic("Tried to read from invalid ipr %d\n", idx); break; } @@ -286,13 +286,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) int break_ipl = -1; #endif -Fault +void AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) { uint64_t old; if (tc->misspeculating()) - return NoFault; + return; switch (idx) { case AlphaISA::IPR_PALtemp0: @@ -443,7 +443,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) case AlphaISA::IPR_ITB_PTE_TEMP: case AlphaISA::IPR_DTB_PTE_TEMP: // read-only registers - return new UnimplementedOpcodeFault; + panic("Tried to write read only ipr %d\n", idx); case AlphaISA::IPR_HWINT_CLR: case AlphaISA::IPR_SL_XMIT: @@ -547,11 +547,10 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) default: // invalid IPR - return new UnimplementedOpcodeFault; + panic("Tried to write to invalid ipr %d\n", idx); } // no error... - return NoFault; } diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index f5483d9c0..fcf022ce1 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -629,7 +629,7 @@ decode OPCODE default Unknown::unknown() { /* Rb is a fake dependency so here is a fun way to get * the parser to understand that. */ - Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0); + Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0); #else Ra = curTick; @@ -681,7 +681,7 @@ decode OPCODE default Unknown::unknown() { 0x00: CallPal::call_pal({{ if (!palValid || (palPriv - && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { + && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) { // invalid pal function code, or attempt to do privileged // PAL call in non-kernel mode fault = new UnimplementedOpcodeFault; @@ -693,7 +693,7 @@ decode OPCODE default Unknown::unknown() { if (dopal) { xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); - NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset; + NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset; } } }}, IsNonSpeculative); @@ -751,7 +751,7 @@ decode OPCODE default Unknown::unknown() { miscRegIndex >= NumInternalProcRegs) fault = new UnimplementedOpcodeFault; else - Ra = xc->readMiscRegWithEffect(miscRegIndex, fault); + Ra = xc->readMiscRegWithEffect(miscRegIndex); }}, IsIprAccess); } } diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa index b4339a1b7..103f85775 100644 --- a/src/arch/alpha/isa/fp.isa +++ b/src/arch/alpha/isa/fp.isa @@ -46,7 +46,7 @@ output exec {{ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) { Fault fault = NoFault; // dummy... this ipr access should not fault - if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) { + if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) { fault = new FloatEnableFault; } return fault; diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 8980fcb40..e806adbcb 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -122,17 +122,16 @@ namespace AlphaISA MiscReg readReg(int misc_reg); - MiscReg readRegWithEffect(int misc_reg, Fault &fault, - ThreadContext *tc); + MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc); //These functions should be removed once the simplescalar cpu model //has been replaced. int getInstAsid(); int getDataAsid(); - Fault setReg(int misc_reg, const MiscReg &val); + void setReg(int misc_reg, const MiscReg &val); - Fault setRegWithEffect(int misc_reg, const MiscReg &val, + void setRegWithEffect(int misc_reg, const MiscReg &val, ThreadContext *tc); void clear() @@ -153,9 +152,9 @@ namespace AlphaISA InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs private: - InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc); + InternalProcReg readIpr(int idx, ThreadContext *tc); - Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc); + void setIpr(int idx, InternalProcReg val, ThreadContext *tc); #endif friend class RegFile; }; @@ -225,22 +224,20 @@ namespace AlphaISA return miscRegFile.readReg(miscReg); } - MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ThreadContext *tc) + MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc) { - fault = NoFault; - return miscRegFile.readRegWithEffect(miscReg, fault, tc); + return miscRegFile.readRegWithEffect(miscReg, tc); } - Fault setMiscReg(int miscReg, const MiscReg &val) + void setMiscReg(int miscReg, const MiscReg &val) { - return miscRegFile.setReg(miscReg, val); + miscRegFile.setReg(miscReg, val); } - Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + void setMiscRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, tc); + miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatReg readFloatReg(int floatReg) @@ -263,26 +260,24 @@ namespace AlphaISA return readFloatRegBits(floatReg); } - Fault setFloatReg(int floatReg, const FloatReg &val) + void setFloatReg(int floatReg, const FloatReg &val) { floatRegFile.d[floatReg] = val; - return NoFault; } - Fault setFloatReg(int floatReg, const FloatReg &val, int width) + void setFloatReg(int floatReg, const FloatReg &val, int width) { - return setFloatReg(floatReg, val); + setFloatReg(floatReg, val); } - Fault setFloatRegBits(int floatReg, const FloatRegBits &val) + void setFloatRegBits(int floatReg, const FloatRegBits &val) { floatRegFile.q[floatReg] = val; - return NoFault; } - Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + void setFloatRegBits(int floatReg, const FloatRegBits &val, int width) { - return setFloatRegBits(floatReg, val); + setFloatRegBits(floatReg, val); } IntReg readIntReg(int intReg) @@ -290,9 +285,9 @@ namespace AlphaISA return intRegFile.readReg(intReg); } - Fault setIntReg(int intReg, const IntReg &val) + void setIntReg(int intReg, const IntReg &val) { - return intRegFile.setReg(intReg, val); + intRegFile.setReg(intReg, val); } void serialize(std::ostream &os); diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index a4527a203..368925e00 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -220,20 +220,20 @@ namespace MipsISA return miscRegFile[misc_reg]; } - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc) + MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc) { return miscRegFile[misc_reg]; } - Fault setReg(int misc_reg, const MiscReg &val) + void setReg(int misc_reg, const MiscReg &val) { - miscRegFile[misc_reg] = val; return NoFault; + miscRegFile[misc_reg] = val; } - Fault setRegWithEffect(int misc_reg, const MiscReg &val, + void setRegWithEffect(int misc_reg, const MiscReg &val, ThreadContext *tc) { - miscRegFile[misc_reg] = val; return NoFault; + miscRegFile[misc_reg] = val; } friend class RegFile; diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index 3a18c681b..dee883c4a 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -62,22 +62,20 @@ namespace MipsISA return miscRegFile.readReg(miscReg); } - MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ThreadContext *tc) + MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc) { - fault = NoFault; - return miscRegFile.readRegWithEffect(miscReg, fault, tc); + return miscRegFile.readRegWithEffect(miscReg, tc); } - Fault setMiscReg(int miscReg, const MiscReg &val) + void setMiscReg(int miscReg, const MiscReg &val) { - return miscRegFile.setReg(miscReg, val); + miscRegFile.setReg(miscReg, val); } - Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + void setMiscRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, tc); + miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatRegVal readFloatReg(int floatReg) @@ -100,24 +98,24 @@ namespace MipsISA return floatRegFile.readRegBits(floatReg,width); } - Fault setFloatReg(int floatReg, const FloatRegVal &val) + void setFloatReg(int floatReg, const FloatRegVal &val) { - return floatRegFile.setReg(floatReg, val, SingleWidth); + floatRegFile.setReg(floatReg, val, SingleWidth); } - Fault setFloatReg(int floatReg, const FloatRegVal &val, int width) + void setFloatReg(int floatReg, const FloatRegVal &val, int width) { - return floatRegFile.setReg(floatReg, val, width); + floatRegFile.setReg(floatReg, val, width); } - Fault setFloatRegBits(int floatReg, const FloatRegBits &val) + void setFloatRegBits(int floatReg, const FloatRegBits &val) { - return floatRegFile.setRegBits(floatReg, val, SingleWidth); + floatRegFile.setRegBits(floatReg, val, SingleWidth); } - Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + void setFloatRegBits(int floatReg, const FloatRegBits &val, int width) { - return floatRegFile.setRegBits(floatReg, val, width); + floatRegFile.setRegBits(floatReg, val, width); } IntReg readIntReg(int intReg) @@ -125,9 +123,9 @@ namespace MipsISA return intRegFile.readReg(intReg); } - Fault setIntReg(int intReg, const IntReg &val) + void setIntReg(int intReg, const IntReg &val) { - return intRegFile.setReg(intReg, val); + intRegFile.setReg(intReg, val); } protected: diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index a64ff09bb..a5f43367d 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -353,14 +353,14 @@ decode OP default Unknown::unknown() 0x1: Nop::membar({{/*stuff*/}}); } default: rdasr({{ - Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); + Rd = xc->readMiscRegWithEffect(RS1 + AsrStart); }}); } 0x29: HPriv::rdhpr({{ - Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); + Rd = xc->readMiscRegWithEffect(RS1 + HprStart); }}); 0x2A: Priv::rdpr({{ - Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); + Rd = xc->readMiscRegWithEffect(RS1 + PrStart); }}); 0x2B: BasicOperate::flushw({{ if(NWindows - 2 - Cansave == 0) diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index bf4572878..2f3cfb417 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -59,20 +59,21 @@ string SparcISA::getMiscRegName(RegIndex index) //XXX These need an implementation someplace /** Fullsystem only register version of ReadRegWithEffect() */ -MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); +MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext *tc); /** Fullsystem only register version of SetRegWithEffect() */ -Fault MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, +void MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc); #endif void MiscRegFile::reset() { - pstateFields.pef = 0; //No FPU + //pstateFields.pef = 0; //No FPU //pstateFields.pef = 1; //FPU #if FULL_SYSTEM //For SPARC, when a system is first started, there is a power //on reset Trap which sets the processor into the following state. //Bits that aren't set aren't defined on startup. + //XXX this code should be moved into the POR fault. tl = MaxTL; gl = MaxGL; @@ -98,22 +99,6 @@ void MiscRegFile::reset() hintp = 0; // no interrupts pending hstick_cmprFields.int_dis = 1; // disable timer compare interrupts hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing -#else -/* //This sets up the initial state of the processor for usermode processes - pstateFields.priv = 0; //Process runs in user mode - pstateFields.ie = 1; //Interrupts are enabled - fsrFields.rd = 0; //Round to nearest - fsrFields.tem = 0; //Floating point traps not enabled - fsrFields.ns = 0; //Non standard mode off - fsrFields.qne = 0; //Floating point queue is empty - fsrFields.aexc = 0; //No accrued exceptions - fsrFields.cexc = 0; //No current exceptions - - //Register window management registers - otherwin = 0; //No windows contain info from other programs - canrestore = 0; //There are no windows to pop - cansave = MaxTL - 2; //All windows are available to save into - cleanwin = MaxTL;*/ #endif } @@ -337,6 +322,30 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) } } +inline void MiscRegFile::setImplicitAsis() +{ + //The spec seems to use trap level to indicate the privilege level of the + //processor. It's unclear whether the implicit ASIs should directly depend + //on the trap level, or if they should really be based on the privelege + //bits + if(tl == 0) + { + implicitInstAsi = implicitDataAsi = + pstateFields.cle ? ASI_PRIMARY_LITTLE : ASI_PRIMARY; + } + else if(tl <= MaxPTL) + { + implicitInstAsi = ASI_NUCLEUS; + implicitDataAsi = pstateFields.cle ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS; + } + else + { + //This is supposed to force physical addresses to match the spec. + //It might not because of context values and partition values. + implicitInstAsi = implicitDataAsi = ASI_REAL; + } +} + void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { @@ -352,6 +361,14 @@ void MiscRegFile::setRegWithEffect(int miscReg, case MISCREG_PCR: //Set up performance counting based on pcr value break; + case MISCREG_PSTATE: + pstate = val; + setImplicitAsis(); + return; + case MISCREG_TL: + tl = val; + setImplicitAsis(); + return; case MISCREG_CWP: tc->changeRegFileContext(CONTEXT_CWP, val); break; @@ -389,6 +406,8 @@ void MiscRegFile::serialize(std::ostream & os) SERIALIZE_ARRAY(htstate, MaxTL); SERIALIZE_SCALAR(htba); SERIALIZE_SCALAR(hstick_cmpr); + SERIALIZE_SCALAR((int)implicitInstAsi); + SERIALIZE_SCALAR((int)implicitDataAsi); } void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) @@ -418,5 +437,10 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) UNSERIALIZE_ARRAY(htstate, MaxTL); UNSERIALIZE_SCALAR(htba); UNSERIALIZE_SCALAR(hstick_cmpr); + int temp; + UNSERIALIZE_SCALAR(temp); + implicitInstAsi = (ASI)temp; + UNSERIALIZE_SCALAR(temp); + implicitDataAsi = (ASI)temp; } diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index 771cb1ed6..ac1ad90b9 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -32,9 +32,11 @@ #ifndef __ARCH_SPARC_MISCREGFILE_HH__ #define __ARCH_SPARC_MISCREGFILE_HH__ +#include "arch/sparc/asi.hh" #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/types.hh" +#include "cpu/cpuevent.hh" #include @@ -329,6 +331,9 @@ namespace SparcISA } fsrFields; }; + ASI implicitInstAsi; + ASI implicitDataAsi; + // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM @@ -374,6 +379,16 @@ namespace SparcISA void setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc); + ASI getInstAsid() + { + return implicitInstAsi; + } + + ASI getDataAsid() + { + return implicitDataAsi; + } + void serialize(std::ostream & os); void unserialize(Checkpoint * cp, const std::string & section); @@ -385,6 +400,7 @@ namespace SparcISA bool isHyperPriv() { return hpstateFields.hpriv; } bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; } bool isNonPriv() { return !isPriv(); } + inline void setImplicitAsis(); }; } diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 5eb874d39..65e6017da 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -79,24 +79,20 @@ MiscReg RegFile::readMiscReg(int miscReg) return miscRegFile.readReg(miscReg); } -MiscReg RegFile::readMiscRegWithEffect(int miscReg, - Fault &fault, ThreadContext *tc) +MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc) { - fault = NoFault; return miscRegFile.readRegWithEffect(miscReg, tc); } -Fault RegFile::setMiscReg(int miscReg, const MiscReg &val) +void RegFile::setMiscReg(int miscReg, const MiscReg &val) { miscRegFile.setReg(miscReg, val); - return NoFault; } -Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val, +void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { miscRegFile.setRegWithEffect(miscReg, val, tc); - return NoFault; } FloatReg RegFile::readFloatReg(int floatReg, int width) @@ -122,27 +118,26 @@ FloatRegBits RegFile::readFloatRegBits(int floatReg) FloatRegFile::SingleWidth); } -Fault RegFile::setFloatReg(int floatReg, const FloatReg &val, int width) +void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width) { - return floatRegFile.setReg(floatReg, val, width); + floatRegFile.setReg(floatReg, val, width); } -Fault RegFile::setFloatReg(int floatReg, const FloatReg &val) +void RegFile::setFloatReg(int floatReg, const FloatReg &val) { //Use the "natural" width of a single float - return setFloatReg(floatReg, val, FloatRegFile::SingleWidth); + setFloatReg(floatReg, val, FloatRegFile::SingleWidth); } -Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) +void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) { - return floatRegFile.setRegBits(floatReg, val, width); + floatRegFile.setRegBits(floatReg, val, width); } -Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) +void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) { //Use the "natural" width of a single float - return floatRegFile.setRegBits(floatReg, val, - FloatRegFile::SingleWidth); + floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth); } IntReg RegFile::readIntReg(int intReg) @@ -150,9 +145,9 @@ IntReg RegFile::readIntReg(int intReg) return intRegFile.readReg(intReg); } -Fault RegFile::setIntReg(int intReg, const IntReg &val) +void RegFile::setIntReg(int intReg, const IntReg &val) { - return intRegFile.setReg(intReg, val); + intRegFile.setReg(intReg, val); } void RegFile::serialize(std::ostream &os) diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 500fbbba4..9f33435f6 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -32,7 +32,6 @@ #ifndef __ARCH_SPARC_REGFILE_HH__ #define __ARCH_SPARC_REGFILE_HH__ -#include "arch/sparc/faults.hh" #include "arch/sparc/floatregfile.hh" #include "arch/sparc/intregfile.hh" #include "arch/sparc/isa_traits.hh" @@ -76,14 +75,23 @@ namespace SparcISA MiscReg readMiscReg(int miscReg); - MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ThreadContext *tc); + MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc); - Fault setMiscReg(int miscReg, const MiscReg &val); + void setMiscReg(int miscReg, const MiscReg &val); - Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + void setMiscRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc); + ASI instAsid() + { + return miscRegFile.getInstAsid(); + } + + ASI dataAsid() + { + return miscRegFile.getDataAsid(); + } + FloatReg readFloatReg(int floatReg, int width); FloatReg readFloatReg(int floatReg); @@ -92,17 +100,17 @@ namespace SparcISA FloatRegBits readFloatRegBits(int floatReg); - Fault setFloatReg(int floatReg, const FloatReg &val, int width); + void setFloatReg(int floatReg, const FloatReg &val, int width); - Fault setFloatReg(int floatReg, const FloatReg &val); + void setFloatReg(int floatReg, const FloatReg &val); - Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width); + void setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - Fault setFloatRegBits(int floatReg, const FloatRegBits &val); + void setFloatRegBits(int floatReg, const FloatRegBits &val); IntReg readIntReg(int intReg); - Fault setIntReg(int intReg, const IntReg &val); + void setIntReg(int intReg, const IntReg &val); void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 35ff08b43..0d42e2c97 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -31,5 +31,33 @@ #ifndef __ARCH_SPARC_TLB_HH__ #define __ARCH_SPARC_TLB_HH__ +#include "sim/faults.hh" + +class ThreadContext; + +namespace SparcISA +{ + class TLB + { + }; + + class ITB : public TLB + { + public: + Fault translate(RequestPtr &req, ThreadContext *tc) const + { + return NoFault; + } + }; + + class DTB : public TLB + { + public: + Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const + { + return NoFault; + } + }; +} #endif // __ARCH_SPARC_TLB_HH__ -- cgit v1.2.3 From 6f78d494101e0ebd542d8fe836df21d104374c33 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Nov 2006 18:46:18 -0500 Subject: Fix a range check on the ipr_index. --HG-- extra : convert_revision : 84e25abd4bb2de0c877c883804d39feb019c7030 --- src/arch/alpha/isa/decoder.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index fcf022ce1..be6f574a9 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -745,7 +745,7 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mfpr(); format HwMoveIPR { 1: hw_mfpr({{ - int miscRegIndex = (ipr_index < NumInternalProcRegs) ? + int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? IprToMiscRegIndex[ipr_index] : -1; if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || miscRegIndex >= NumInternalProcRegs) @@ -760,7 +760,7 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mtpr(); format HwMoveIPR { 1: hw_mtpr({{ - int miscRegIndex = (ipr_index < NumInternalProcRegs) ? + int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? IprToMiscRegIndex[ipr_index] : -1; if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || miscRegIndex >= NumInternalProcRegs) -- cgit v1.2.3 From ccaf80cc46fb86639ab5ee166baca08277f5450f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 2 Nov 2006 13:11:38 -0500 Subject: Use ISA specific makeExtMI. src/arch/alpha/utility.hh: For now makeExtMI will be specific to the ISA. --HG-- extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496 --- src/arch/alpha/utility.hh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 0304d1c3a..cb86c7e9e 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -43,11 +43,11 @@ namespace AlphaISA { static inline ExtMachInst - makeExtMI(MachInst inst, ThreadContext * xc) { + makeExtMI(MachInst inst, Addr pc) { #if FULL_SYSTEM ExtMachInst ext_inst = inst; - if (xc->readPC() && 0x1) - return ext_inst|=(static_cast(xc->readPC() & 0x1) << 32); + if (pc && 0x1) + return ext_inst|=(static_cast(pc & 0x1) << 32); else return ext_inst; #else -- cgit v1.2.3 From fa918329000c3661a4c6840f952c3247522eb826 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 01:15:31 -0500 Subject: Fixed a comment --HG-- extra : convert_revision : bebc701508e1d38ee74a07377c634d5e46e89abe --- src/arch/sparc/asi.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/sparc/asi.hh b/src/arch/sparc/asi.hh index 876567225..6677b23df 100644 --- a/src/arch/sparc/asi.hh +++ b/src/arch/sparc/asi.hh @@ -219,4 +219,4 @@ namespace SparcISA }; -#endif // __ARCH_SPARC_TLB_HH__ +#endif // __ARCH_SPARC_ASI_HH__ -- cgit v1.2.3 From c8fc116c7636893517254f785707eba1726d3265 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 02:25:39 -0500 Subject: Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the --HG-- extra : convert_revision : c535000a6a170caefd441687b60f940513d29739 --- src/arch/SConscript | 1 + src/arch/alpha/interrupts.hh | 171 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 172 insertions(+) create mode 100644 src/arch/alpha/interrupts.hh (limited to 'src/arch') diff --git a/src/arch/SConscript b/src/arch/SConscript index dda1dea53..092fad225 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -49,6 +49,7 @@ sources = [] isa_switch_hdrs = Split(''' arguments.hh faults.hh + interrupts.hh isa_traits.hh locked_mem.hh process.hh diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh new file mode 100644 index 000000000..2f031f434 --- /dev/null +++ b/src/arch/alpha/interrupts.hh @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Kevin Lim + */ + +#ifndef __ARCH_ALPHA_INTERRUPT_HH__ +#define __ARCH_ALPHA_INTERRUPT_HH__ + +#include "arch/alpha/faults.hh" +#include "arch/alpha/isa_traits.hh" +#include "cpu/thread_context.hh" + +namespace AlphaISA +{ + class Interrupts + { + protected: + uint64_t interrupts[NumInterruptLevels]; + uint64_t intstatus; + + public: + Interrupts() + { + memset(interrupts, 0, sizeof(interrupts)); + intstatus = 0; + } + + void post(int int_num, int index) + { + DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); + + if (int_num < 0 || int_num >= NumInterruptLevels) + panic("int_num out of bounds\n"); + + if (index < 0 || index >= sizeof(uint64_t) * 8) + panic("int_num out of bounds\n"); + + interrupts[int_num] |= 1 << index; + intstatus |= (ULL(1) << int_num); + } + + void clear(int int_num, int index) + { + DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); + + if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) + panic("int_num out of bounds\n"); + + if (index < 0 || index >= sizeof(uint64_t) * 8) + panic("int_num out of bounds\n"); + + interrupts[int_num] &= ~(1 << index); + if (interrupts[int_num] == 0) + intstatus &= ~(ULL(1) << int_num); + } + + void clear_all() + { + DPRINTF(Interrupt, "Interrupts all cleared\n"); + + memset(interrupts, 0, sizeof(interrupts)); + intstatus = 0; + } + + bool check_interrupt(int int_num) const { + if (int_num > NumInterruptLevels) + panic("int_num out of bounds\n"); + + return interrupts[int_num] != 0; + } + + bool check_interrupts() const { return intstatus != 0; } + + void serialize(std::ostream &os) + { + SERIALIZE_ARRAY(interrupts, NumInterruptLevels); + SERIALIZE_SCALAR(intstatus); + } + + void unserialize(Checkpoint *cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); + UNSERIALIZE_SCALAR(intstatus); + } + + Fault getInterrupt(ThreadContext * tc) + { + int ipl = 0; + int summary = 0; + + if (tc->readMiscReg(IPR_ASTRR)) + panic("asynchronous traps not implemented\n"); + + if (tc->readMiscReg(IPR_SIRR)) { + for (int i = INTLEVEL_SOFTWARE_MIN; + i < INTLEVEL_SOFTWARE_MAX; i++) { + if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { + // See table 4-19 of 21164 hardware reference + ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; + summary |= (ULL(1) << i); + } + } + } + + uint64_t interrupts = intstatus; + if (interrupts) { + for (int i = INTLEVEL_EXTERNAL_MIN; + i < INTLEVEL_EXTERNAL_MAX; i++) { + if (interrupts & (ULL(1) << i)) { + // See table 4-19 of 21164 hardware reference + ipl = i; + summary |= (ULL(1) << i); + } + } + } + + if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) { + tc->setMiscReg(IPR_ISR, summary); + tc->setMiscReg(IPR_INTID, ipl); + + /* The following needs to be added back in somehow */ + // Checker needs to know these two registers were updated. +/*#if USE_CHECKER + if (this->checker) { + this->checker->threadBase()->setMiscReg(IPR_ISR, summary); + this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); + } +#endif*/ + + DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", + tc->readMiscReg(IPR_IPLR), ipl, summary); + + return new InterruptFault; + } else { + return NoFault; + } + } + + private: + uint64_t intr_status() const { return intstatus; } + }; +} + +#endif + -- cgit v1.2.3 From 118b9dc1f9e84a12ea26743f6cec1eac5b4ab13a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 04:25:33 -0500 Subject: Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however. --HG-- extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b --- src/arch/alpha/ev5.cc | 2 +- src/arch/alpha/faults.cc | 2 +- src/arch/alpha/interrupts.hh | 15 +++++---------- 3 files changed, 7 insertions(+), 12 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 314b445e0..dca948bbd 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -147,7 +147,7 @@ AlphaISA::zeroRegisters(CPU *cpu) Fault SimpleThread::hwrei() { - if (!inPalMode()) + if (!(readPC() & 0x3)) return new UnimplementedOpcodeFault; setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 7179bf025..5efcf92e4 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -125,7 +125,7 @@ void AlphaFault::invoke(ThreadContext * tc) countStat()++; // exception restart address - if (setRestartAddress() || !tc->inPalMode()) + if (setRestartAddress() || !(tc->readPC() & 0x3)) tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC()); if (skipFaultingInstruction()) { diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh index 2f031f434..75031ae47 100644 --- a/src/arch/alpha/interrupts.hh +++ b/src/arch/alpha/interrupts.hh @@ -88,15 +88,6 @@ namespace AlphaISA intstatus = 0; } - bool check_interrupt(int int_num) const { - if (int_num > NumInterruptLevels) - panic("int_num out of bounds\n"); - - return interrupts[int_num] != 0; - } - - bool check_interrupts() const { return intstatus != 0; } - void serialize(std::ostream &os) { SERIALIZE_ARRAY(interrupts, NumInterruptLevels); @@ -109,6 +100,11 @@ namespace AlphaISA UNSERIALIZE_SCALAR(intstatus); } + bool check_interrupts(ThreadContext * tc) const + { + return (intstatus != 0) && !(tc->readPC() & 0x3); + } + Fault getInterrupt(ThreadContext * tc) { int ipl = 0; @@ -163,7 +159,6 @@ namespace AlphaISA } private: - uint64_t intr_status() const { return intstatus; } }; } -- cgit v1.2.3 From 7c5a859243d681407d7cfa99835271e6d3b90338 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 10:52:08 -0500 Subject: removed ua2005.cc since it's been obsorbed into the miscregfile, and added system.cc --HG-- extra : convert_revision : 2a124adcefe0d15860632a05e8788d3fd34008c2 --- src/arch/sparc/SConscript | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index e317502e0..5843058a4 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -54,8 +54,8 @@ base_sources = Split(''' # Full-system sources full_system_sources = Split(''' - ua2005.cc vtophys.cc + system.cc ''') # Syscall emulation (non-full-system) sources -- cgit v1.2.3 From 694323b7c4922d0591598a0a501ff17f312c5307 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 10:54:34 -0500 Subject: Move around misc reg code src/arch/sparc/faults.cc: Moved some code here from miscregfile.cc src/arch/sparc/miscregfile.cc: Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc src/arch/sparc/miscregfile.hh: readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect. --HG-- extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb --- src/arch/sparc/faults.cc | 36 ++++++++++- src/arch/sparc/miscregfile.cc | 143 +++++++++++++++++++++++++++++------------- src/arch/sparc/miscregfile.hh | 6 -- 3 files changed, 134 insertions(+), 51 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 567ca5f5c..6bca6adc5 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -33,12 +33,13 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/process.hh" #include "base/bitfield.hh" #include "base/trace.hh" +#include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" #if !FULL_SYSTEM +#include "arch/sparc/process.hh" #include "mem/page_table.hh" #include "sim/process.hh" #endif @@ -361,6 +362,39 @@ void SparcFault::invoke(ThreadContext * tc) //Use the SPARC trap state machine } +void PowerOnReset::invoke(ThreadContext * tc) +{ + //For SPARC, when a system is first started, there is a power + //on reset Trap which sets the processor into the following state. + //Bits that aren't set aren't defined on startup. + /* + tl = MaxTL; + gl = MaxGL; + + tickFields.counter = 0; //The TICK register is unreadable bya + tickFields.npt = 1; //The TICK register is unreadable by by !priv + + softint = 0; // Clear all the soft interrupt bits + tick_cmprFields.int_dis = 1; // disable timer compare interrupts + tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing + stickFields.npt = 1; //The TICK register is unreadable by by !priv + stick_cmprFields.int_dis = 1; // disable timer compare interrupts + stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing + + tt[tl] = _trapType; + pstate = 0; // fields 0 but pef + pstateFields.pef = 1; + + hpstate = 0; + hpstateFields.red = 1; + hpstateFields.hpriv = 1; + hpstateFields.tlz = 0; // this is a guess + hintp = 0; // no interrupts pending + hstick_cmprFields.int_dis = 1; // disable timer compare interrupts + hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing + */ +} + #endif #if !FULL_SYSTEM diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 2f3cfb417..a66e40717 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -31,9 +31,14 @@ #include "arch/sparc/miscregfile.hh" #include "base/trace.hh" +#include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" +#if FULL_SYSTEM +#include "arch/sparc/system.hh" +#endif + using namespace SparcISA; using namespace std; @@ -55,51 +60,8 @@ string SparcISA::getMiscRegName(RegIndex index) return miscRegName[index]; } -#if FULL_SYSTEM - -//XXX These need an implementation someplace -/** Fullsystem only register version of ReadRegWithEffect() */ -MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext *tc); -/** Fullsystem only register version of SetRegWithEffect() */ -void MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, - ThreadContext * tc); -#endif - void MiscRegFile::reset() { - //pstateFields.pef = 0; //No FPU - //pstateFields.pef = 1; //FPU -#if FULL_SYSTEM - //For SPARC, when a system is first started, there is a power - //on reset Trap which sets the processor into the following state. - //Bits that aren't set aren't defined on startup. - //XXX this code should be moved into the POR fault. - tl = MaxTL; - gl = MaxGL; - - tickFields.counter = 0; //The TICK register is unreadable bya - tickFields.npt = 1; //The TICK register is unreadable by by !priv - - softint = 0; // Clear all the soft interrupt bits - tick_cmprFields.int_dis = 1; // disable timer compare interrupts - tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing - stickFields.npt = 1; //The TICK register is unreadable by by !priv - stick_cmprFields.int_dis = 1; // disable timer compare interrupts - stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing - - - tt[tl] = power_on_reset; - pstate = 0; // fields 0 but pef - pstateFields.pef = 1; - - hpstate = 0; - hpstateFields.red = 1; - hpstateFields.hpriv = 1; - hpstateFields.tlz = 0; // this is a guess - hintp = 0; // no interrupts pending - hstick_cmprFields.int_dis = 1; // disable timer compare interrupts - hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing -#endif } MiscReg MiscRegFile::readReg(int miscReg) @@ -199,10 +161,20 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) case MISCREG_PCR: case MISCREG_PIC: panic("Performance Instrumentation not impl\n"); - /** Floating Point Status Register */ case MISCREG_FSR: panic("Floating Point not implemented\n"); +//We'll include this only in FS so we don't need the SparcSystem type around +//in SE. +#if FULL_SYSTEM + case MISCREG_STICK: + SparcSystem *sys; + sys = dynamic_cast(tc->getSystemPtr()); + assert(sys != NULL); + return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; +#endif + case MISCREG_HVER: + return NWindows | MaxTL << 8 | MaxGL << 16; } return readReg(miscReg); } @@ -350,6 +322,10 @@ void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { const uint64_t Bit64 = (1ULL << 63); + uint64_t time; +#if FULL_SYSTEM + SparcSystem *sys; +#endif switch (miscReg) { case MISCREG_TICK: tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64; @@ -375,6 +351,68 @@ void MiscRegFile::setRegWithEffect(int miscReg, case MISCREG_GL: tc->changeRegFileContext(CONTEXT_GLOBALS, val); break; + case MISCREG_SOFTINT: + //We need to inject interrupts, and or notify the interrupt + //object that it needs to use a different interrupt level. + //Any newly appropriate interrupts will happen when the cpu gets + //around to checking for them. This might not be quite what we + //want. + break; + case MISCREG_SOFTINT_CLR: + //Do whatever this is supposed to do... + break; + case MISCREG_SOFTINT_SET: + //Do whatever this is supposed to do... + break; + case MISCREG_TICK_CMPR: + if (tickCompare == NULL) + tickCompare = new TickCompareEvent(this, tc); + setReg(miscReg, val); + if (tick_cmprFields.int_dis && tickCompare->scheduled()) + tickCompare->deschedule(); + time = tick_cmprFields.tick_cmpr - tickFields.counter; + if (!tick_cmprFields.int_dis && time > 0) + tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + break; + case MISCREG_PIL: + //We need to inject interrupts, and or notify the interrupt + //object that it needs to use a different interrupt level. + //Any newly appropriate interrupts will happen when the cpu gets + //around to checking for them. This might not be quite what we + //want. + break; +//We'll include this only in FS so we don't need the SparcSystem type around +//in SE. +#if FULL_SYSTEM + case MISCREG_STICK: + sys = dynamic_cast(tc->getSystemPtr()); + assert(sys != NULL); + sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; + stickFields.npt = val & Bit64 ? 1 : 0; + break; + case MISCREG_STICK_CMPR: + if (sTickCompare == NULL) + sTickCompare = new STickCompareEvent(this, tc); + sys = dynamic_cast(tc->getSystemPtr()); + assert(sys != NULL); + if (stick_cmprFields.int_dis && sTickCompare->scheduled()) + sTickCompare->deschedule(); + time = stick_cmprFields.tick_cmpr - sys->sysTick; + if (!stick_cmprFields.int_dis && time > 0) + sTickCompare->schedule(time * Clock::Int::ns); + break; + case MISCREG_HSTICK_CMPR: + if (hSTickCompare == NULL) + hSTickCompare = new HSTickCompareEvent(this, tc); + sys = dynamic_cast(tc->getSystemPtr()); + assert(sys != NULL); + if (hstick_cmprFields.int_dis && hSTickCompare->scheduled()) + hSTickCompare->deschedule(); + int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; + if (!hstick_cmprFields.int_dis && time > 0) + hSTickCompare->schedule(time * Clock::Int::ns); + break; +#endif } setReg(miscReg, val); } @@ -444,3 +482,20 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) implicitDataAsi = (ASI)temp; } +void +MiscRegFile::processTickCompare(ThreadContext *tc) +{ + panic("tick compare not implemented\n"); +} + +void +MiscRegFile::processSTickCompare(ThreadContext *tc) +{ + panic("tick compare not implemented\n"); +} + +void +MiscRegFile::processHSTickCompare(ThreadContext *tc) +{ + panic("tick compare not implemented\n"); +} diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index ac1ad90b9..0e424dbd2 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -354,12 +354,6 @@ namespace SparcISA typedef CpuEventWrapper HSTickCompareEvent; HSTickCompareEvent *hSTickCompare; - - /** Fullsystem only register version of ReadRegWithEffect() */ - MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); - /** Fullsystem only register version of SetRegWithEffect() */ - Fault setFSRegWithEffect(int miscReg, const MiscReg &val, - ThreadContext * tc); #endif public: -- cgit v1.2.3 From e6fed44625802bd185cfbbf9808624f792637d43 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 10:55:29 -0500 Subject: Add an invoke function for PowerOnReset --HG-- extra : convert_revision : a1cdd35c74f6e85f42a04061b466ec7617da8ac2 --- src/arch/sparc/faults.hh | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 394a06294..c087365a2 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -130,6 +130,7 @@ class PowerOnReset : public SparcFault TrapType trapType() {return _trapType;} FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} + void invoke(ThreadContext * tc); }; class WatchDogReset : public SparcFault -- cgit v1.2.3 From ab651344dda9ba09c1c3e1855a5bbc250bdc5ea0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 10:56:47 -0500 Subject: Add the syscall number as the second parameter for the trap fault. This could be improved and syscalls could be called from the trap's invoke method. --HG-- extra : convert_revision : 127a3673a076110fb3605c0fbc93e8d7e9fec84b --- src/arch/sparc/isa/decoder.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index a5f43367d..33352cb2c 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -726,7 +726,7 @@ decode OP default Unknown::unknown() #if FULL_SYSTEM int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); - fault = new TrapInstruction(lTrapNum); + fault = new TrapInstruction(lTrapNum, R1); #else DPRINTF(Sparc, "The syscall number is %d\n", R1); xc->syscall(R1); @@ -739,7 +739,7 @@ decode OP default Unknown::unknown() #if FULL_SYSTEM int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); - fault = new TrapInstruction(lTrapNum); + fault = new TrapInstruction(lTrapNum, R1); #else DPRINTF(Sparc, "The syscall number is %d\n", R1); xc->syscall(R1); -- cgit v1.2.3 From 6b701a6d25f16e0e1b146fb2ce9277f53fbdbbc5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 11:03:03 -0500 Subject: Compilation fixes. --HG-- extra : convert_revision : 44d67a3bb95f875f17586499aa4a04268aa2fd46 --- src/arch/sparc/system.cc | 13 ++++++++----- src/arch/sparc/system.hh | 2 +- 2 files changed, 9 insertions(+), 6 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index ef6443d17..952ac2deb 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -77,7 +77,7 @@ SparcSystem::SparcSystem(Params *p) hypervisor->loadSections(&functionalPort, SparcISA::LoadAddrMask); // load symbols - if (!reset->loadGlobalSymbols(reset)) + if (!reset->loadGlobalSymbols(resetSymtab)) panic("could not load reset symbols\n"); if (!openboot->loadGlobalSymbols(openbootSymtab)) @@ -148,7 +148,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem) Param hypervisor_bin; Param openboot_bin; + Param boot_cpu_frequency; Param boot_osflags; + Param system_type; + Param system_rev; Param readfile; Param init_param; @@ -156,7 +159,6 @@ END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem) BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem) - INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), INIT_PARAM(physmem, "phsyical memory"), INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)", System::MemoryModeStrings), @@ -164,12 +166,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem) INIT_PARAM(reset_bin, "file that contains the reset code"), INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"), INIT_PARAM(openboot_bin, "file that contains the openboot code"), + INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", "a"), - INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), - INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0), INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34), - INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10) + INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10), + INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), + INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0) END_INIT_SIM_OBJECT_PARAMS(SparcSystem) diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh index 614707f6c..3c8c6327e 100644 --- a/src/arch/sparc/system.hh +++ b/src/arch/sparc/system.hh @@ -46,7 +46,7 @@ class SparcSystem : public System struct Params : public System::Params { std::string reset_bin; - std::string hypervison_bin; + std::string hypervisor_bin; std::string openboot_bin; std::string boot_osflags; uint64_t system_type; -- cgit v1.2.3 From 3f4b098985e5544d2fb2ef74004d2c3359936097 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 11:04:10 -0500 Subject: Added a stub initCPU function. This would be a good place to force in a PowerOnReset fault to kick start the CPU. --HG-- extra : convert_revision : 79e1fa2ef40e326682069639e260db255fd29d93 --- src/arch/sparc/utility.hh | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/arch') diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 23fddf0e9..d8880e317 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -99,6 +99,12 @@ namespace SparcISA template void zeroRegisters(TC *tc); + void initCPU(ThreadContext *tc, int cpuId) + { + //This would be a good place to stick a PowerOnReset fault into the + //cpu. + } + } // namespace SparcISA #endif -- cgit v1.2.3 From 29a79acb7c1b1c6614134f00097487d6baeed15b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 11:05:13 -0500 Subject: Gutted out the old Alpha stuff. --HG-- extra : convert_revision : 6767dc1305a58e3e7eb0ee909d54768e51744927 --- src/arch/sparc/vtophys.cc | 132 ++++++++-------------------------------------- 1 file changed, 22 insertions(+), 110 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc index f7fd92c15..429126b70 100644 --- a/src/arch/sparc/vtophys.cc +++ b/src/arch/sparc/vtophys.cc @@ -32,135 +32,47 @@ #include -#include "arch/alpha/ev5.hh" -#include "arch/alpha/vtophys.hh" +#include "arch/sparc/vtophys.hh" #include "base/chunk_generator.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" #include "mem/vport.hh" using namespace std; -using namespace AlphaISA; -AlphaISA::PageTableEntry -AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr) +namespace SparcISA { - Addr level1_pte = ptbr + vaddr.level1(); - AlphaISA::PageTableEntry level1 = mem->read(level1_pte); - if (!level1.valid()) { - DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); - return 0; + PageTableEntry kernel_pte_lookup(FunctionalPort *mem, + Addr ptbr, VAddr vaddr) + { + PageTableEntry pte(4); + return pte; } - Addr level2_pte = level1.paddr() + vaddr.level2(); - AlphaISA::PageTableEntry level2 = mem->read(level2_pte); - if (!level2.valid()) { - DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); - return 0; + Addr vtophys(Addr vaddr) + { + return vaddr; } - Addr level3_pte = level2.paddr() + vaddr.level3(); - AlphaISA::PageTableEntry level3 = mem->read(level3_pte); - if (!level3.valid()) { - DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); - return 0; + Addr vtophys(ThreadContext *tc, Addr addr) + { + return addr; } - return level3; -} -Addr -AlphaISA::vtophys(Addr vaddr) -{ - Addr paddr = 0; - if (AlphaISA::IsUSeg(vaddr)) - DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); - else if (AlphaISA::IsK0Seg(vaddr)) - paddr = AlphaISA::K0Seg2Phys(vaddr); - else - panic("vtophys: ptbr is not set on virtual lookup"); - DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); - - return paddr; -} - -Addr -AlphaISA::vtophys(ThreadContext *tc, Addr addr) -{ - AlphaISA::VAddr vaddr = addr; - Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20); - Addr paddr = 0; - //@todo Andrew couldn't remember why he commented some of this code - //so I put it back in. Perhaps something to do with gdb debugging? - if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) { - paddr = vaddr & ~ULL(1); - } else { - if (AlphaISA::IsK0Seg(vaddr)) { - paddr = AlphaISA::K0Seg2Phys(vaddr); - } else if (!ptbr) { - paddr = vaddr; - } else { - AlphaISA::PageTableEntry pte = - kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); - if (pte.valid()) - paddr = pte.paddr() | vaddr.offset(); - } + void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) + { } + void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) + { + } - DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); - - return paddr; -} - - -void -AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) -{ - uint8_t *dst = (uint8_t *)dest; - VirtualPort *vp = tc->getVirtPort(tc); - - vp->readBlob(src, dst, cplen); - - tc->delVirtPort(vp); - -} - -void -AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) -{ - uint8_t *src = (uint8_t *)source; - VirtualPort *vp = tc->getVirtPort(tc); - - vp->writeBlob(dest, src, cplen); - - tc->delVirtPort(vp); -} - -void -AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) -{ - int len = 0; - VirtualPort *vp = tc->getVirtPort(tc); - - do { - vp->readBlob(vaddr++, (uint8_t*)dst++, 1); - len++; - } while (len < maxlen && dst[len] != 0 ); - - tc->delVirtPort(vp); - dst[len] = 0; -} + void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) + { + } -void -AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) -{ - VirtualPort *vp = tc->getVirtPort(tc); - for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); - gen.next()) + void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) { - vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); - src += gen.size(); } - tc->delVirtPort(vp); } -- cgit v1.2.3 From 6ad386f1a8df96c9679dcffb326420b240e98c05 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 14:40:35 -0500 Subject: Calling syscalls from within the trap instruction's invoke method won't work because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this. --HG-- extra : convert_revision : 1805c9244cfd62d0ee7862d8fd7c9983e00c5747 --- src/arch/sparc/faults.cc | 5 ----- src/arch/sparc/faults.hh | 7 +------ src/arch/sparc/isa/decoder.isa | 4 ++-- 3 files changed, 3 insertions(+), 13 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 6bca6adc5..da7fc730d 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -399,11 +399,6 @@ void PowerOnReset::invoke(ThreadContext * tc) #if !FULL_SYSTEM -void TrapInstruction::invoke(ThreadContext * tc) -{ - // Should be handled in ISA. -} - void SpillNNormal::invoke(ThreadContext *tc) { doNormalFault(tc, trapType()); diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index c087365a2..0c7106707 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -604,17 +604,12 @@ class TrapInstruction : public EnumeratedFault static TrapType _baseTrapType; static FaultPriority _priority; static FaultStat _count; - uint64_t syscall_num; TrapType baseTrapType() {return _baseTrapType;} public: - TrapInstruction(uint32_t n, uint64_t syscall) : - EnumeratedFault(n), syscall_num(syscall) {;} + TrapInstruction(int32_t n) : EnumeratedFault(n) {;} FaultName name() {return _name;} FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} -#if !FULL_SYSTEM - void invoke(ThreadContext * tc); -#endif }; diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 33352cb2c..a5f43367d 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -726,7 +726,7 @@ decode OP default Unknown::unknown() #if FULL_SYSTEM int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); - fault = new TrapInstruction(lTrapNum, R1); + fault = new TrapInstruction(lTrapNum); #else DPRINTF(Sparc, "The syscall number is %d\n", R1); xc->syscall(R1); @@ -739,7 +739,7 @@ decode OP default Unknown::unknown() #if FULL_SYSTEM int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); - fault = new TrapInstruction(lTrapNum, R1); + fault = new TrapInstruction(lTrapNum); #else DPRINTF(Sparc, "The syscall number is %d\n", R1); xc->syscall(R1); -- cgit v1.2.3 From 8778d85b2d352fdbfbbf077332790f94852b20d3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 14:41:27 -0500 Subject: Use a PowerOnReset to initialize the cpu. --HG-- extra : convert_revision : 9e65af095c37c7c67db377424d2d4363fa8065f9 --- src/arch/sparc/utility.hh | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index d8880e317..e2b0b2307 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -31,6 +31,7 @@ #ifndef __ARCH_SPARC_UTILITY_HH__ #define __ARCH_SPARC_UTILITY_HH__ +#include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "base/misc.hh" #include "base/bitfield.hh" @@ -99,10 +100,10 @@ namespace SparcISA template void zeroRegisters(TC *tc); - void initCPU(ThreadContext *tc, int cpuId) + inline void initCPU(ThreadContext *tc, int cpuId) { - //This would be a good place to stick a PowerOnReset fault into the - //cpu. + static Fault por = new PowerOnReset(); + por->invoke(tc); } } // namespace SparcISA -- cgit v1.2.3 From 601822c6b507f6c3145eacf8f9db216522f70733 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 14:42:12 -0500 Subject: Make things compile in SE again. --HG-- extra : convert_revision : cf7faf5001b31d61c61ddce2386d61c919075800 --- src/arch/sparc/miscregfile.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index a66e40717..217fba0bd 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -322,8 +322,8 @@ void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { const uint64_t Bit64 = (1ULL << 63); - uint64_t time; #if FULL_SYSTEM + uint64_t time; SparcSystem *sys; #endif switch (miscReg) { @@ -364,6 +364,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, case MISCREG_SOFTINT_SET: //Do whatever this is supposed to do... break; +#if FULL_SYSTEM case MISCREG_TICK_CMPR: if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); @@ -374,6 +375,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, if (!tick_cmprFields.int_dis && time > 0) tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); break; +#endif case MISCREG_PIL: //We need to inject interrupts, and or notify the interrupt //object that it needs to use a different interrupt level. @@ -482,6 +484,7 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) implicitDataAsi = (ASI)temp; } +#if FULL_SYSTEM void MiscRegFile::processTickCompare(ThreadContext *tc) { @@ -499,3 +502,4 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } +#endif -- cgit v1.2.3 From 21cf4a46b9e9ce52266aac873aa107cad82cc847 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 4 Nov 2006 21:41:01 -0500 Subject: fixes so that M5 will compile under solaris SConstruct: Add check to see if we need to include libsocket src/arch/sparc/floatregfile.cc: src/arch/sparc/intregfile.cc: use memset rather than bzero and include the appropriate headerfile src/base/pollevent.cc: If we're compling under solaris we need sys/file.h src/base/random.cc: src/base/random.hh: solaris doesn't have random(), so use rint with the correct rounding mode if we're compiling on solaris src/base/stats/flags.hh: u_int32_t?? src/base/time.hh: grab the timersub() define from freebsd since it doesn't exist in solaris src/cpu/inst_seq.hh: we don't need to include stdint here src/sim/byteswap.hh: the method to detect endianness on Solaris is a little more complex... --HG-- extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1 --- src/arch/sparc/floatregfile.cc | 4 +++- src/arch/sparc/intregfile.cc | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc index 3afe6ef54..7f3d5a758 100644 --- a/src/arch/sparc/floatregfile.cc +++ b/src/arch/sparc/floatregfile.cc @@ -34,6 +34,8 @@ #include "sim/byteswap.hh" #include "sim/serialize.hh" +#include + using namespace SparcISA; using namespace std; @@ -55,7 +57,7 @@ string SparcISA::getFloatRegName(RegIndex index) void FloatRegFile::clear() { - bzero(regSpace, sizeof(regSpace)); + memset(regSpace, 0, sizeof(regSpace)); } FloatReg FloatRegFile::readReg(int floatReg, int width) diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc index 164f194dd..0e313dc94 100644 --- a/src/arch/sparc/intregfile.cc +++ b/src/arch/sparc/intregfile.cc @@ -33,6 +33,8 @@ #include "base/trace.hh" #include "sim/serialize.hh" +#include + using namespace SparcISA; using namespace std; @@ -62,7 +64,7 @@ void IntRegFile::clear() for (x = 0; x < MaxGL; x++) memset(regGlobals[x], 0, sizeof(IntReg) * RegsPerFrame); for(int x = 0; x < 2 * NWindows; x++) - bzero(regSegments[x], sizeof(IntReg) * RegsPerFrame); + memset(regSegments[x], 0, sizeof(IntReg) * RegsPerFrame); } IntRegFile::IntRegFile() -- cgit v1.2.3 From 1ffff78ca90d04622da78e7d1212148762bccef6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 6 Nov 2006 18:26:11 -0500 Subject: Created seperate SConscript for the dev directory. Made subdirectories for Alpha and SPARC and put SConscripts in them. --HG-- rename : src/base/kgdb.h => src/arch/alpha/kgdb.h rename : src/dev/alpha_access.h => src/dev/alpha/access.h rename : src/dev/alpha_console.cc => src/dev/alpha/console.cc rename : src/dev/alpha_console.hh => src/dev/alpha/console.hh extra : convert_revision : a7dd466308cb83edc40528689aacb72413089cdf --- src/arch/alpha/kgdb.h | 174 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) create mode 100644 src/arch/alpha/kgdb.h (limited to 'src/arch') diff --git a/src/arch/alpha/kgdb.h b/src/arch/alpha/kgdb.h new file mode 100644 index 000000000..104244d0b --- /dev/null +++ b/src/arch/alpha/kgdb.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratories. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)remote-sl.h 8.1 (Berkeley) 6/11/93 + */ + +/* $NetBSD: kgdb.h,v 1.4 1998/08/13 02:10:59 eeh Exp $ */ + +#ifndef __KGDB_H__ +#define __KGDB_H__ + +/* + * Message types. + */ +#define KGDB_SIGNAL '?' // last sigal +#define KGDB_SET_BAUD 'b' // set baud (deprecated) +#define KGDB_SET_BREAK 'B' // set breakpoint (deprecated) +#define KGDB_CONT 'c' // resume +#define KGDB_ASYNC_CONT 'C' // continue with signal +#define KGDB_DEBUG 'd' // toggle debug flags (deprecated) +#define KGDB_DETACH 'D' // detach remote gdb +#define KGDB_REG_R 'g' // read general registers +#define KGDB_REG_W 'G' // write general registers +#define KGDB_SET_THREAD 'H' // set thread +#define KGDB_CYCLE_STEP 'i' // step a single cycle +#define KGDB_SIG_CYCLE_STEP 'I' // signal then single cycle step +#define KGDB_KILL 'k' // kill program +#define KGDB_MEM_R 'm' // read memory +#define KGDB_MEM_W 'M' // write memory +#define KGDB_READ_REG 'p' // read register +#define KGDB_SET_REG 'P' // write register +#define KGDB_QUERY_VAR 'q' // query variable +#define KGDB_SET_VAR 'Q' // set variable +#define KGDB_RESET 'r' // reset system. (Deprecated) +#define KGDB_STEP 's' // step +#define KGDB_ASYNC_STEP 'S' // signal and step +#define KGDB_THREAD_ALIVE 'T' // find out if the thread is alive. +#define KGDB_TARGET_EXIT 'W' // target exited +#define KGDB_BINARY_DLOAD 'X' // write memory +#define KGDB_CLR_HW_BKPT 'z' // remove breakpoint or watchpoint +#define KGDB_SET_HW_BKPT 'Z' // insert breakpoint or watchpoint + +/* + * start of frame/end of frame + */ +#define KGDB_START '$' +#define KGDB_END '#' +#define KGDB_GOODP '+' +#define KGDB_BADP '-' + +/* + * Stuff for KGDB. + */ +#define KGDB_NUMREGS 66 /* from tm-alpha.h, NUM_REGS */ +#define KGDB_REG_V0 0 +#define KGDB_REG_T0 1 +#define KGDB_REG_T1 2 +#define KGDB_REG_T2 3 +#define KGDB_REG_T3 4 +#define KGDB_REG_T4 5 +#define KGDB_REG_T5 6 +#define KGDB_REG_T6 7 +#define KGDB_REG_T7 8 +#define KGDB_REG_S0 9 +#define KGDB_REG_S1 10 +#define KGDB_REG_S2 11 +#define KGDB_REG_S3 12 +#define KGDB_REG_S4 13 +#define KGDB_REG_S5 14 +#define KGDB_REG_S6 15 /* FP */ +#define KGDB_REG_A0 16 +#define KGDB_REG_A1 17 +#define KGDB_REG_A2 18 +#define KGDB_REG_A3 19 +#define KGDB_REG_A4 20 +#define KGDB_REG_A5 21 +#define KGDB_REG_T8 22 +#define KGDB_REG_T9 23 +#define KGDB_REG_T10 24 +#define KGDB_REG_T11 25 +#define KGDB_REG_RA 26 +#define KGDB_REG_T12 27 +#define KGDB_REG_AT 28 +#define KGDB_REG_GP 29 +#define KGDB_REG_SP 30 +#define KGDB_REG_ZERO 31 +#define KGDB_REG_F0 32 +#define KGDB_REG_F1 33 +#define KGDB_REG_F2 34 +#define KGDB_REG_F3 35 +#define KGDB_REG_F4 36 +#define KGDB_REG_F5 37 +#define KGDB_REG_F6 38 +#define KGDB_REG_F7 39 +#define KGDB_REG_F8 40 +#define KGDB_REG_F9 41 +#define KGDB_REG_F10 42 +#define KGDB_REG_F11 43 +#define KGDB_REG_F12 44 +#define KGDB_REG_F13 45 +#define KGDB_REG_F14 46 +#define KGDB_REG_F15 47 +#define KGDB_REG_F16 48 +#define KGDB_REG_F17 49 +#define KGDB_REG_F18 50 +#define KGDB_REG_F19 51 +#define KGDB_REG_F20 52 +#define KGDB_REG_F21 53 +#define KGDB_REG_F22 54 +#define KGDB_REG_F23 55 +#define KGDB_REG_F24 56 +#define KGDB_REG_F25 57 +#define KGDB_REG_F26 58 +#define KGDB_REG_F27 59 +#define KGDB_REG_F28 60 +#define KGDB_REG_F29 61 +#define KGDB_REG_F30 62 +#define KGDB_REG_F31 63 +#define KGDB_REG_PC 64 +#define KGDB_REG_VFP 65 + +/* Too much? Must be large enough for register transfer. */ +#define KGDB_BUFLEN 1024 + +/* + * Kernel Entry Vectors. [OSF/1 PALcode Specific] + */ + +#define ALPHA_KENTRY_INT 0 +#define ALPHA_KENTRY_ARITH 1 +#define ALPHA_KENTRY_MM 2 +#define ALPHA_KENTRY_IF 3 +#define ALPHA_KENTRY_UNA 4 +#define ALPHA_KENTRY_SYS 5 + +#endif /* __KGDB_H__ */ -- cgit v1.2.3 From e39de58d21723df527ec979cde1df29980fab234 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 6 Nov 2006 18:28:10 -0500 Subject: Took the Alpha prefix off of AlphaArguments, and made sure it was being used from TheISA:: rather than AlphaISA:: --HG-- extra : convert_revision : 17c143d3cbc2f58a7a9d01366a8f649810ff7f33 --- src/arch/alpha/arguments.cc | 6 +++--- src/arch/alpha/arguments.hh | 30 +++++++++++++++--------------- 2 files changed, 18 insertions(+), 18 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/arguments.cc b/src/arch/alpha/arguments.cc index 9f9002003..e89bd70b0 100644 --- a/src/arch/alpha/arguments.cc +++ b/src/arch/alpha/arguments.cc @@ -35,7 +35,7 @@ using namespace AlphaISA; -AlphaArguments::Data::~Data() +Arguments::Data::~Data() { while (!data.empty()) { delete [] data.front(); @@ -44,7 +44,7 @@ AlphaArguments::Data::~Data() } char * -AlphaArguments::Data::alloc(size_t size) +Arguments::Data::alloc(size_t size) { char *buf = new char[size]; data.push_back(buf); @@ -52,7 +52,7 @@ AlphaArguments::Data::alloc(size_t size) } uint64_t -AlphaArguments::getArg(bool fp) +Arguments::getArg(bool fp) { if (number < 6) { if (fp) diff --git a/src/arch/alpha/arguments.hh b/src/arch/alpha/arguments.hh index d977d48d6..c44181a8d 100644 --- a/src/arch/alpha/arguments.hh +++ b/src/arch/alpha/arguments.hh @@ -41,7 +41,7 @@ class ThreadContext; namespace AlphaISA { -class AlphaArguments +class Arguments { protected: ThreadContext *tc; @@ -65,62 +65,62 @@ class AlphaArguments RefCountingPtr data; public: - AlphaArguments(ThreadContext *ctx, int n = 0) + Arguments(ThreadContext *ctx, int n = 0) : tc(ctx), number(n), data(NULL) { assert(number >= 0); data = new Data;} - AlphaArguments(const AlphaArguments &args) + Arguments(const Arguments &args) : tc(args.tc), number(args.number), data(args.data) {} - ~AlphaArguments() {} + ~Arguments() {} ThreadContext *getThreadContext() const { return tc; } - const AlphaArguments &operator=(const AlphaArguments &args) { + const Arguments &operator=(const Arguments &args) { tc = args.tc; number = args.number; data = args.data; return *this; } - AlphaArguments &operator++() { + Arguments &operator++() { ++number; assert(number >= 0); return *this; } - AlphaArguments operator++(int) { - AlphaArguments args = *this; + Arguments operator++(int) { + Arguments args = *this; ++number; assert(number >= 0); return args; } - AlphaArguments &operator--() { + Arguments &operator--() { --number; assert(number >= 0); return *this; } - AlphaArguments operator--(int) { - AlphaArguments args = *this; + Arguments operator--(int) { + Arguments args = *this; --number; assert(number >= 0); return args; } - const AlphaArguments &operator+=(int index) { + const Arguments &operator+=(int index) { number += index; assert(number >= 0); return *this; } - const AlphaArguments &operator-=(int index) { + const Arguments &operator-=(int index) { number -= index; assert(number >= 0); return *this; } - AlphaArguments operator[](int index) { - return AlphaArguments(tc, index); + Arguments operator[](int index) { + return Arguments(tc, index); } template -- cgit v1.2.3 From 85a6079db7c2e7146dc437c9c032d2aa56dd9048 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 6 Nov 2006 18:29:58 -0500 Subject: Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not. --HG-- extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707 --- src/arch/SConscript | 1 + src/arch/alpha/SConscript | 1 + src/arch/alpha/ev5.cc | 2 +- src/arch/alpha/remote_gdb.cc | 424 ++++++++++++++++++++++++++++++++++++++++ src/arch/alpha/remote_gdb.hh | 130 ++++++++++++ src/arch/alpha/system.cc | 2 +- src/arch/sparc/remote_gdb.cc | 456 +++++++++++++++++++++++++++++++++++++++++++ src/arch/sparc/remote_gdb.hh | 129 ++++++++++++ 8 files changed, 1143 insertions(+), 2 deletions(-) create mode 100644 src/arch/alpha/remote_gdb.cc create mode 100644 src/arch/alpha/remote_gdb.hh create mode 100644 src/arch/sparc/remote_gdb.cc create mode 100644 src/arch/sparc/remote_gdb.hh (limited to 'src/arch') diff --git a/src/arch/SConscript b/src/arch/SConscript index 092fad225..2ef3d5ee0 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -54,6 +54,7 @@ isa_switch_hdrs = Split(''' locked_mem.hh process.hh regfile.hh + remote_gdb.hh stacktrace.hh syscallreturn.hh tlb.hh diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 9a5680649..2d733d73b 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -60,6 +60,7 @@ full_system_sources = Split(''' osfpal.cc stacktrace.cc vtophys.cc + remote_gdb.cc system.cc freebsd/system.cc linux/system.cc diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index dca948bbd..6f8f255b4 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -33,7 +33,7 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/osfpal.hh" #include "arch/alpha/tlb.hh" -#include "base/kgdb.h" +#include "arch/alpha/kgdb.h" #include "base/remote_gdb.hh" #include "base/stats/events.hh" #include "config/full_system.hh" diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc new file mode 100644 index 000000000..96c7ea6e2 --- /dev/null +++ b/src/arch/alpha/remote_gdb.cc @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +/* + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratories. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94 + */ + +/*- + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $ + * + * Taken from NetBSD + * + * "Stub" to allow remote cpu to debug over a serial line using gdb. + */ + +#include + +#include +#include + +#include "arch/vtophys.hh" +#include "arch/alpha/remote_gdb.hh" +#include "base/intmath.hh" +#include "base/remote_gdb.hh" +#include "base/socket.hh" +#include "base/trace.hh" +#include "config/full_system.hh" +#include "cpu/thread_context.hh" +#include "cpu/static_inst.hh" +#include "mem/physical.hh" +#include "mem/port.hh" +#include "sim/system.hh" + +using namespace std; +using namespace AlphaISA; + +RemoteGDB::Event::Event(RemoteGDB *g, int fd, int e) + : PollEvent(fd, e), gdb(g) +{} + +void +RemoteGDB::Event::process(int revent) +{ + if (revent & POLLIN) + gdb->trap(ALPHA_KENTRY_IF); + else if (revent & POLLNVAL) + gdb->detach(); +} + +RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) + : BaseRemoteGDB(_system, c, KGDB_NUMREGS), + event(NULL) +{} + +RemoteGDB::~RemoteGDB() +{ + if (event) + delete event; +} + +/////////////////////////////////////////////////////////// +// RemoteGDB::acc +// +// Determine if the mapping at va..(va+len) is valid. +// +bool +RemoteGDB::acc(Addr va, size_t len) +{ + Addr last_va; + + va = TheISA::TruncPage(va); + last_va = TheISA::RoundPage(va + len); + + do { + if (TheISA::IsK0Seg(va)) { + if (va < (TheISA::K0SegBase + pmem->size())) { + DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= " + "%#x < K0SEG + size\n", va); + return true; + } else { + DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n", + va); + return false; + } + } + + /** + * This code says that all accesses to palcode (instruction and data) + * are valid since there isn't a va->pa mapping because palcode is + * accessed physically. At some point this should probably be cleaned up + * but there is no easy way to do it. + */ + + if (AlphaISA::PcPAL(va) || va < 0x10000) + return true; + + Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20); + TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va); + if (!pte.valid()) { + DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); + return false; + } + va += TheISA::PageBytes; + } while (va < last_va); + + DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); + return true; +} + +/////////////////////////////////////////////////////////// +// RemoteGDB::getregs +// +// Translate the kernel debugger register format into +// the GDB register format. +void +RemoteGDB::getregs() +{ + memset(gdbregs.regs, 0, gdbregs.size); + + gdbregs.regs[KGDB_REG_PC] = context->readPC(); + + // @todo: Currently this is very Alpha specific. + if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + gdbregs.regs[i] = context->readIntReg(AlphaISA::reg_redir[i]); + } + } else { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + gdbregs.regs[i] = context->readIntReg(i); + } + } + +#ifdef KGDB_FP_REGS + for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { + gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i); + } +#endif +} + +/////////////////////////////////////////////////////////// +// RemoteGDB::setregs +// +// Translate the GDB register format into the kernel +// debugger register format. +// +void +RemoteGDB::setregs() +{ + // @todo: Currently this is very Alpha specific. + if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + context->setIntReg(AlphaISA::reg_redir[i], gdbregs.regs[i]); + } + } else { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + context->setIntReg(i, gdbregs.regs[i]); + } + } + +#ifdef KGDB_FP_REGS + for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { + context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]); + } +#endif + context->setPC(gdbregs.regs[KGDB_REG_PC]); +} + +void +RemoteGDB::setTempBreakpoint(TempBreakpoint &bkpt, Addr addr) +{ + DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", addr); + + bkpt.address = addr; + insertHardBreak(addr, 4); +} + +void +RemoteGDB::clearTempBreakpoint(TempBreakpoint &bkpt) +{ + DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", + bkpt.address); + + + removeHardBreak(bkpt.address, 4); + bkpt.address = 0; +} + +void +RemoteGDB::clearSingleStep() +{ + DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n", + takenBkpt.address, notTakenBkpt.address); + + if (takenBkpt.address != 0) + clearTempBreakpoint(takenBkpt); + + if (notTakenBkpt.address != 0) + clearTempBreakpoint(notTakenBkpt); +} + +void +RemoteGDB::setSingleStep() +{ + Addr pc = context->readPC(); + Addr npc, bpc; + bool set_bt = false; + + npc = pc + sizeof(MachInst); + + // User was stopped at pc, e.g. the instruction at pc was not + // executed. + MachInst inst = read(pc); + StaticInstPtr si(inst); + if (si->hasBranchTarget(pc, context, bpc)) { + // Don't bother setting a breakpoint on the taken branch if it + // is the same as the next pc + if (bpc != npc) + set_bt = true; + } + + DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n", + takenBkpt.address, notTakenBkpt.address); + + setTempBreakpoint(notTakenBkpt, npc); + + if (set_bt) + setTempBreakpoint(takenBkpt, bpc); +} + +// Write bytes to kernel address space for debugger. +bool +RemoteGDB::write(Addr vaddr, size_t size, const char *data) +{ + if (BaseRemoteGDB::write(vaddr, size, data)) { +#ifdef IMB + alpha_pal_imb(); +#endif + return true; + } else { + return false; + } +} + + +PCEventQueue *RemoteGDB::getPcEventQueue() +{ + return &system->pcEventQueue; +} + + +RemoteGDB::HardBreakpoint::HardBreakpoint(RemoteGDB *_gdb, Addr pc) + : PCEvent(_gdb->getPcEventQueue(), "HardBreakpoint Event", pc), + gdb(_gdb), refcount(0) +{ + DPRINTF(GDBMisc, "creating hardware breakpoint at %#x\n", evpc); +} + +void +RemoteGDB::HardBreakpoint::process(ThreadContext *tc) +{ + DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc()); + + if (tc == gdb->context) + gdb->trap(ALPHA_KENTRY_INT); +} + +bool +RemoteGDB::insertSoftBreak(Addr addr, size_t len) +{ + if (len != sizeof(MachInst)) + panic("invalid length\n"); + + return insertHardBreak(addr, len); +} + +bool +RemoteGDB::removeSoftBreak(Addr addr, size_t len) +{ + if (len != sizeof(MachInst)) + panic("invalid length\n"); + + return removeHardBreak(addr, len); +} + +bool +RemoteGDB::insertHardBreak(Addr addr, size_t len) +{ + if (len != sizeof(MachInst)) + panic("invalid length\n"); + + DPRINTF(GDBMisc, "inserting hardware breakpoint at %#x\n", addr); + + HardBreakpoint *&bkpt = hardBreakMap[addr]; + if (bkpt == 0) + bkpt = new HardBreakpoint(this, addr); + + bkpt->refcount++; + + return true; +} + +bool +RemoteGDB::removeHardBreak(Addr addr, size_t len) +{ + if (len != sizeof(MachInst)) + panic("invalid length\n"); + + DPRINTF(GDBMisc, "removing hardware breakpoint at %#x\n", addr); + + break_iter_t i = hardBreakMap.find(addr); + if (i == hardBreakMap.end()) + return false; + + HardBreakpoint *hbp = (*i).second; + if (--hbp->refcount == 0) { + delete hbp; + hardBreakMap.erase(i); + } + + return true; +} diff --git a/src/arch/alpha/remote_gdb.hh b/src/arch/alpha/remote_gdb.hh new file mode 100644 index 000000000..1dd4ada38 --- /dev/null +++ b/src/arch/alpha/remote_gdb.hh @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#ifndef __ARCH_ALPHA_REMOTE_GDB_HH__ +#define __ARCH_ALPHA_REMOTE_GDB_HH__ + +#include + +#include "arch/alpha/types.hh" +#include "arch/alpha/kgdb.h" +#include "base/remote_gdb.hh" +#include "cpu/pc_event.hh" +#include "base/pollevent.hh" +#include "base/socket.hh" + +class System; +class ThreadContext; +class PhysicalMemory; + +namespace AlphaISA +{ + class RemoteGDB : public BaseRemoteGDB + { + private: + friend void debugger(); + friend class GDBListener; + + protected: + class Event : public PollEvent + { + protected: + RemoteGDB *gdb; + + public: + Event(RemoteGDB *g, int fd, int e); + void process(int revent); + }; + + friend class Event; + Event *event; + + protected: + // Machine memory + bool write(Addr addr, size_t size, const char *data); + + public: + RemoteGDB(System *system, ThreadContext *context); + ~RemoteGDB(); + + bool acc(Addr addr, size_t len); + + protected: + void getregs(); + void setregs(); + + void clearSingleStep(); + void setSingleStep(); + + PCEventQueue *getPcEventQueue(); + + protected: + class HardBreakpoint : public PCEvent + { + private: + RemoteGDB *gdb; + + public: + int refcount; + + public: + HardBreakpoint(RemoteGDB *_gdb, Addr addr); + std::string name() { return gdb->name() + ".hwbkpt"; } + + virtual void process(ThreadContext *tc); + }; + friend class HardBreakpoint; + + typedef std::map break_map_t; + typedef break_map_t::iterator break_iter_t; + break_map_t hardBreakMap; + + bool insertSoftBreak(Addr addr, size_t len); + bool removeSoftBreak(Addr addr, size_t len); + bool insertHardBreak(Addr addr, size_t len); + bool removeHardBreak(Addr addr, size_t len); + + protected: + struct TempBreakpoint { + Addr address; // set here + MachInst bkpt_inst; // saved instruction at bkpt + int init_count; // number of times to skip bkpt + int count; // current count + }; + + TempBreakpoint notTakenBkpt; + TempBreakpoint takenBkpt; + + void clearTempBreakpoint(TempBreakpoint &bkpt); + void setTempBreakpoint(TempBreakpoint &bkpt, Addr addr); + }; +} + +#endif /* __ARCH_ALPHA_REMOTE_GDB_H__ */ diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc index 5597eaedc..710f6ef46 100644 --- a/src/arch/alpha/system.cc +++ b/src/arch/alpha/system.cc @@ -31,8 +31,8 @@ #include "arch/alpha/ev5.hh" #include "arch/alpha/system.hh" +#include "arch/alpha/remote_gdb.hh" #include "arch/vtophys.hh" -#include "base/remote_gdb.hh" #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "base/trace.hh" diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc new file mode 100644 index 000000000..2e662af7f --- /dev/null +++ b/src/arch/sparc/remote_gdb.cc @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +/* + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratories. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94 + */ + +/*- + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $ + * + * Taken from NetBSD + * + * "Stub" to allow remote cpu to debug over a serial line using gdb. + */ + +#include + +#include +#include + +#include "arch/vtophys.hh" +#include "arch/sparc/remote_gdb.hh" +#include "base/intmath.hh" +#include "base/kgdb.h" +#include "base/remote_gdb.hh" +#include "base/socket.hh" +#include "base/trace.hh" +#include "config/full_system.hh" +#include "cpu/thread_context.hh" +#include "cpu/static_inst.hh" +#include "mem/physical.hh" +#include "mem/port.hh" +#include "sim/system.hh" + +using namespace std; +using namespace TheISA; + +RemoteGDB::Event::Event(RemoteGDB *g, int fd, int e) + : PollEvent(fd, e), gdb(g) +{} + +void +RemoteGDB::Event::process(int revent) +{ + if (revent & POLLIN) + gdb->trap(ALPHA_KENTRY_IF); + else if (revent & POLLNVAL) + gdb->detach(); +} + +RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) + : BaseRemoteGDB(_system, c, KGDB_NUMREGS), + event(NULL) +{} + +RemoteGDB::~RemoteGDB() +{ + if (event) + delete event; +} + +/////////////////////////////////////////////////////////// +// RemoteGDB::acc +// +// Determine if the mapping at va..(va+len) is valid. +// +bool +RemoteGDB::acc(Addr va, size_t len) +{ + Addr last_va; + + va = TheISA::TruncPage(va); + last_va = TheISA::RoundPage(va + len); + + do { + if (TheISA::IsK0Seg(va)) { + if (va < (TheISA::K0SegBase + pmem->size())) { + DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= " + "%#x < K0SEG + size\n", va); + return true; + } else { + DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n", + va); + return false; + } + } + + /** + * This code says that all accesses to palcode (instruction and data) + * are valid since there isn't a va->pa mapping because palcode is + * accessed physically. At some point this should probably be cleaned up + * but there is no easy way to do it. + */ + + if (AlphaISA::PcPAL(va) || va < 0x10000) + return true; + + Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20); + TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va); + if (!pte.valid()) { + DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); + return false; + } + va += TheISA::PageBytes; + } while (va < last_va); + + DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); + return true; +} + +/////////////////////////////////////////////////////////// +// RemoteGDB::signal +// +// Translate a trap number into a Unix-compatible signal number. +// (GDB only understands Unix signal numbers.) +// +int +RemoteGDB::signal(int type) +{ + switch (type) { + case ALPHA_KENTRY_INT: + return (SIGTRAP); + + case ALPHA_KENTRY_UNA: + return (SIGBUS); + + case ALPHA_KENTRY_ARITH: + return (SIGFPE); + + case ALPHA_KENTRY_IF: + return (SIGILL); + + case ALPHA_KENTRY_MM: + return (SIGSEGV); + + default: + panic("unknown signal type"); + return 0; + } +} + +/////////////////////////////////////////////////////////// +// RemoteGDB::getregs +// +// Translate the kernel debugger register format into +// the GDB register format. +void +RemoteGDB::getregs() +{ + memset(gdbregs.regs, 0, gdbregs.size); + + gdbregs.regs[KGDB_REG_PC] = context->readPC(); + + // @todo: Currently this is very Alpha specific. + if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + gdbregs.regs[i] = context->readIntReg(AlphaISA::reg_redir[i]); + } + } else { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + gdbregs.regs[i] = context->readIntReg(i); + } + } + +#ifdef KGDB_FP_REGS + for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { + gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i); + } +#endif +} + +/////////////////////////////////////////////////////////// +// RemoteGDB::setregs +// +// Translate the GDB register format into the kernel +// debugger register format. +// +void +RemoteGDB::setregs() +{ + // @todo: Currently this is very Alpha specific. + if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + context->setIntReg(AlphaISA::reg_redir[i], gdbregs.regs[i]); + } + } else { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + context->setIntReg(i, gdbregs.regs[i]); + } + } + +#ifdef KGDB_FP_REGS + for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { + context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]); + } +#endif + context->setPC(gdbregs.regs[KGDB_REG_PC]); +} + +void +RemoteGDB::setTempBreakpoint(TempBreakpoint &bkpt, Addr addr) +{ + DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", addr); + + bkpt.address = addr; + insertHardBreak(addr, 4); +} + +void +RemoteGDB::clearTempBreakpoint(TempBreakpoint &bkpt) +{ + DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", + bkpt.address); + + + removeHardBreak(bkpt.address, 4); + bkpt.address = 0; +} + +void +RemoteGDB::clearSingleStep() +{ + DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n", + takenBkpt.address, notTakenBkpt.address); + + if (takenBkpt.address != 0) + clearTempBreakpoint(takenBkpt); + + if (notTakenBkpt.address != 0) + clearTempBreakpoint(notTakenBkpt); +} + +void +RemoteGDB::setSingleStep() +{ + Addr pc = context->readPC(); + Addr npc, bpc; + bool set_bt = false; + + npc = pc + sizeof(MachInst); + + // User was stopped at pc, e.g. the instruction at pc was not + // executed. + MachInst inst = read(pc); + StaticInstPtr si(inst); + if (si->hasBranchTarget(pc, context, bpc)) { + // Don't bother setting a breakpoint on the taken branch if it + // is the same as the next pc + if (bpc != npc) + set_bt = true; + } + + DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n", + takenBkpt.address, notTakenBkpt.address); + + setTempBreakpoint(notTakenBkpt, npc); + + if (set_bt) + setTempBreakpoint(takenBkpt, bpc); +} + +// Write bytes to kernel address space for debugger. +bool +RemoteGDB::write(Addr vaddr, size_t size, const char *data) +{ + if (BaseRemoteGDB::write(vaddr, size, data)) { +#ifdef IMB + alpha_pal_imb(); +#endif + return true; + } else { + return false; + } +} + + +PCEventQueue *RemoteGDB::getPcEventQueue() +{ + return &system->pcEventQueue; +} + + +RemoteGDB::HardBreakpoint::HardBreakpoint(RemoteGDB *_gdb, Addr pc) + : PCEvent(_gdb->getPcEventQueue(), "HardBreakpoint Event", pc), + gdb(_gdb), refcount(0) +{ + DPRINTF(GDBMisc, "creating hardware breakpoint at %#x\n", evpc); +} + +void +RemoteGDB::HardBreakpoint::process(ThreadContext *tc) +{ + DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc()); + + if (tc == gdb->context) + gdb->trap(ALPHA_KENTRY_INT); +} + +bool +RemoteGDB::insertSoftBreak(Addr addr, size_t len) +{ + if (len != sizeof(MachInst)) + panic("invalid length\n"); + + return insertHardBreak(addr, len); +} + +bool +RemoteGDB::removeSoftBreak(Addr addr, size_t len) +{ + if (len != sizeof(MachInst)) + panic("invalid length\n"); + + return removeHardBreak(addr, len); +} + +bool +RemoteGDB::insertHardBreak(Addr addr, size_t len) +{ + if (len != sizeof(MachInst)) + panic("invalid length\n"); + + DPRINTF(GDBMisc, "inserting hardware breakpoint at %#x\n", addr); + + HardBreakpoint *&bkpt = hardBreakMap[addr]; + if (bkpt == 0) + bkpt = new HardBreakpoint(this, addr); + + bkpt->refcount++; + + return true; +} + +bool +RemoteGDB::removeHardBreak(Addr addr, size_t len) +{ + if (len != sizeof(MachInst)) + panic("invalid length\n"); + + DPRINTF(GDBMisc, "removing hardware breakpoint at %#x\n", addr); + + break_iter_t i = hardBreakMap.find(addr); + if (i == hardBreakMap.end()) + return false; + + HardBreakpoint *hbp = (*i).second; + if (--hbp->refcount == 0) { + delete hbp; + hardBreakMap.erase(i); + } + + return true; +} diff --git a/src/arch/sparc/remote_gdb.hh b/src/arch/sparc/remote_gdb.hh new file mode 100644 index 000000000..6ac4f296f --- /dev/null +++ b/src/arch/sparc/remote_gdb.hh @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#ifndef __ARCH_ALPHA_REMOTE_GDB_HH__ +#define __ARCH_ALPHA_REMOTE_GDB_HH__ + +#include + +#include "arch/types.hh" +#include "base/remote_gdb.hh" +#include "cpu/pc_event.hh" +#include "base/pollevent.hh" + +class System; +class ThreadContext; +class PhysicalMemory; + +namespace SparcISA +{ + class RemoteGDB : public BaseRemoteGDB + { + private: + friend void debugger(); + friend class GDBListener; + + protected: + class Event : public PollEvent + { + protected: + RemoteGDB *gdb; + + public: + Event(RemoteGDB *g, int fd, int e); + void process(int revent); + }; + + friend class Event; + Event *event; + + protected: + // Machine memory + bool write(Addr addr, size_t size, const char *data); + + public: + RemoteGDB(System *system, ThreadContext *context); + ~RemoteGDB(); + + bool acc(Addr addr, size_t len); + int signal(int type); + + protected: + void getregs(); + void setregs(); + + void clearSingleStep(); + void setSingleStep(); + + PCEventQueue *getPcEventQueue(); + + protected: + class HardBreakpoint : public PCEvent + { + private: + RemoteGDB *gdb; + + public: + int refcount; + + public: + HardBreakpoint(RemoteGDB *_gdb, Addr addr); + std::string name() { return gdb->name() + ".hwbkpt"; } + + virtual void process(ThreadContext *tc); + }; + friend class HardBreakpoint; + + typedef std::map break_map_t; + typedef break_map_t::iterator break_iter_t; + break_map_t hardBreakMap; + + bool insertSoftBreak(Addr addr, size_t len); + bool removeSoftBreak(Addr addr, size_t len); + bool insertHardBreak(Addr addr, size_t len); + bool removeHardBreak(Addr addr, size_t len); + + protected: + struct TempBreakpoint { + Addr address; // set here + MachInst bkpt_inst; // saved instruction at bkpt + int init_count; // number of times to skip bkpt + int count; // current count + }; + + TempBreakpoint notTakenBkpt; + TempBreakpoint takenBkpt; + + void clearTempBreakpoint(TempBreakpoint &bkpt); + void setTempBreakpoint(TempBreakpoint &bkpt, Addr addr); + }; +} + +#endif /* __ARCH_ALPHA_REMOTE_GDB_H__ */ -- cgit v1.2.3 From ef1a92eb9b372ffadb7985941797ba37b61beac5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 6 Nov 2006 18:30:28 -0500 Subject: Stub for SPARC interrupt handling object. --HG-- extra : convert_revision : 7257e3387c01e84e5a1018a9cdcc09a79edfa934 --- src/arch/sparc/interrupts.hh | 92 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 src/arch/sparc/interrupts.hh (limited to 'src/arch') diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh new file mode 100644 index 000000000..0072f4184 --- /dev/null +++ b/src/arch/sparc/interrupts.hh @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_SPARC_INTERRUPT_HH__ +#define __ARCH_SPARC_INTERRUPT_HH__ + +#include "arch/sparc/faults.hh" + +namespace SparcISA +{ + class Interrupts + { + protected: + Fault interrupts[NumInterruptLevels]; + bool requested[NumInterruptLevels]; + + public: + Interrupts() + { + for(int x = 0; x < NumInterruptLevels; x++) + { + interrupts[x] = new InterruptLevelN(x); + requested[x] = false; + } + } + void post(int int_num, int index) + { + if(int_num < 0 || int_num >= NumInterruptLevels) + panic("int_num out of bounds\n"); + + requested[int_num] = true; + } + + void clear(int int_num, int index) + { + requested[int_num] = false; + } + + void clear_all() + { + for(int x = 0; x < NumInterruptLevels; x++) + requested[x] = false; + } + + bool check_interrupts(ThreadContext * tc) const + { + return true; + } + + Fault getInterrupt(ThreadContext * tc) + { + return NoFault; + } + + void serialize(std::ostream &os) + { + } + + void unserialize(Checkpoint *cp, const std::string §ion) + { + } + }; +} + +#endif // __ARCH_SPARC_INTERRUPT_HH__ -- cgit v1.2.3 From b04a2653f941fd8174760da156b601bf8a2de2ef Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 6 Nov 2006 19:09:23 -0500 Subject: Got rid of obsolete ivlb and ivle psuedo instructions. --HG-- extra : convert_revision : c3c2dd5a6e7181ad94194146d7fa2b33b21074fb --- src/arch/alpha/isa/decoder.isa | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index be6f574a9..7014d4c22 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -795,12 +795,6 @@ decode OPCODE default Unknown::unknown() { 0x04: quiesceTime({{ R0 = AlphaPseudo::quiesceTime(xc->tcBase()); }}, IsNonSpeculative, IsUnverifiable); - 0x10: ivlb({{ - AlphaPseudo::ivlb(xc->tcBase()); - }}, No_OpClass, IsNonSpeculative); - 0x11: ivle({{ - AlphaPseudo::ivle(xc->tcBase()); - }}, No_OpClass, IsNonSpeculative); 0x20: m5exit_old({{ AlphaPseudo::m5exit_old(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); -- cgit v1.2.3 From eb4ef3ad763cf95a6437f9a88b1ab38255f5dcc3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:33:21 -0500 Subject: Made kern a switching header file directory. SConstruct: Put the code to make a switching header directory into a function so they are easy to make. src/arch/SConscript: Replace switching header code with the new function call. src/kern/SConscript: Created a new switching header directory in kern, and moved the declaration of some source files here. --HG-- rename : src/kern/kernel_stats.cc => src/kern/base_kernel_stats.cc rename : src/kern/kernel_stats.hh => src/kern/base_kernel_stats.hh extra : convert_revision : 98f5320a5ade567c3e4f67fef123dfb0c5122545 --- src/arch/SConscript | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) (limited to 'src/arch') diff --git a/src/arch/SConscript b/src/arch/SConscript index 2ef3d5ee0..82a56d4eb 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -63,36 +63,8 @@ isa_switch_hdrs = Split(''' vtophys.hh ''') -# Generate the header. target[0] is the full path of the output -# header to generate. 'source' is a dummy variable, since we get the -# list of ISAs from env['ALL_ISA_LIST']. -def gen_switch_hdr(target, source, env): - fname = str(target[0]) - basename = os.path.basename(fname) - f = open(fname, 'w') - f.write('#include "arch/isa_specific.hh"\n') - cond = '#if' - for isa in env['ALL_ISA_LIST']: - f.write('%s THE_ISA == %s_ISA\n#include "arch/%s/%s"\n' - % (cond, isa.upper(), isa, basename)) - cond = '#elif' - f.write('#else\n#error "THE_ISA not set"\n#endif\n') - f.close() - return 0 - -# String to print when generating header -def gen_switch_hdr_string(target, source, env): - return "Generating ISA switch header " + str(target[0]) - -# Build SCons Action object. 'varlist' specifies env vars that this -# action depends on; when env['ALL_ISA_LIST'] changes these actions -# should get re-executed. -switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string, - varlist=['ALL_ISA_LIST']) - -# Instantiate actions for each header -for hdr in isa_switch_hdrs: - env.Command(hdr, [], switch_hdr_action) +# Set up this directory to support switching headers +env.make_switching_dir('arch', isa_switch_hdrs, env) ################################################################# # -- cgit v1.2.3 From 4bfb8547bbdee3bd0ec23ae067ff04fd5e07f4be Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:36:54 -0500 Subject: Moved the switched version of kernel_stats.hh back to kern, and moved the base kernel_stats to base_kernel_stats --HG-- extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017 --- src/arch/alpha/ev5.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 6f8f255b4..76574e2df 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -40,7 +40,7 @@ #include "cpu/base.hh" #include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" -#include "kern/kernel_stats.hh" +#include "kern/alpha/kernel_stats.hh" #include "sim/debug.hh" #include "sim/sim_exit.hh" @@ -379,10 +379,10 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) case AlphaISA::IPR_DTB_CM: if (val & 0x18) { if (tc->getKernelStats()) - tc->getKernelStats()->mode(Kernel::user, tc); + tc->getKernelStats()->mode(TheISA::Kernel::user, tc); } else { if (tc->getKernelStats()) - tc->getKernelStats()->mode(Kernel::kernel, tc); + tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc); } case AlphaISA::IPR_ICM: -- cgit v1.2.3 From da24915181516740e94efc7de4d9e9263c663e0d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:38:33 -0500 Subject: Moved the idle event out of system_events.hh. The skipFuncEvent can be made ISA independent by making it use the #define for branch delay slots (and NNPC) --HG-- extra : convert_revision : b2631b1163397ecc99f2f315e2b88537e2002731 --- src/arch/alpha/linux/system.cc | 1 + src/arch/alpha/linux/system.hh | 1 + 2 files changed, 2 insertions(+) (limited to 'src/arch') diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index 7cf234eeb..00684edbb 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -49,6 +49,7 @@ #include "cpu/thread_context.hh" #include "cpu/base.hh" #include "dev/platform.hh" +#include "kern/alpha/idle_event.hh" #include "kern/linux/printk.hh" #include "kern/linux/events.hh" #include "mem/physical.hh" diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh index 6921ba820..d4c92ac01 100644 --- a/src/arch/alpha/linux/system.hh +++ b/src/arch/alpha/linux/system.hh @@ -39,6 +39,7 @@ class BreakPCEvent; class IdleStartEvent; #include "arch/alpha/system.hh" +#include "kern/alpha/idle_event.hh" #include "kern/linux/events.hh" using namespace AlphaISA; -- cgit v1.2.3 From 54e22bfe9591ef6e83613757dd43c4cce2255cef Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:39:40 -0500 Subject: Broke remote_gdb into a base class and architecture specific derived classes. --HG-- extra : convert_revision : 8c528fab56a95b8245ad0f2572d62bb556ce0dde --- src/arch/alpha/remote_gdb.cc | 137 +++----------------------- src/arch/alpha/remote_gdb.hh | 60 +----------- src/arch/sparc/remote_gdb.cc | 222 +++++-------------------------------------- src/arch/sparc/remote_gdb.hh | 80 ++++------------ 4 files changed, 54 insertions(+), 445 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index 96c7ea6e2..829e41ca8 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -121,8 +121,9 @@ #include #include -#include "arch/vtophys.hh" +#include "arch/alpha/kgdb.h" #include "arch/alpha/remote_gdb.hh" +#include "arch/vtophys.hh" #include "base/intmath.hh" #include "base/remote_gdb.hh" #include "base/socket.hh" @@ -135,30 +136,12 @@ #include "sim/system.hh" using namespace std; -using namespace AlphaISA; - -RemoteGDB::Event::Event(RemoteGDB *g, int fd, int e) - : PollEvent(fd, e), gdb(g) -{} - -void -RemoteGDB::Event::process(int revent) -{ - if (revent & POLLIN) - gdb->trap(ALPHA_KENTRY_IF); - else if (revent & POLLNVAL) - gdb->detach(); -} +using namespace TheISA; RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) - : BaseRemoteGDB(_system, c, KGDB_NUMREGS), - event(NULL) -{} - -RemoteGDB::~RemoteGDB() + : BaseRemoteGDB(_system, c, KGDB_NUMREGS) { - if (event) - delete event; + memset(gdbregs.regs, 0, gdbregs.size); } /////////////////////////////////////////////////////////// @@ -268,36 +251,16 @@ RemoteGDB::setregs() context->setPC(gdbregs.regs[KGDB_REG_PC]); } -void -RemoteGDB::setTempBreakpoint(TempBreakpoint &bkpt, Addr addr) -{ - DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", addr); - - bkpt.address = addr; - insertHardBreak(addr, 4); -} - -void -RemoteGDB::clearTempBreakpoint(TempBreakpoint &bkpt) -{ - DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", - bkpt.address); - - - removeHardBreak(bkpt.address, 4); - bkpt.address = 0; -} - void RemoteGDB::clearSingleStep() { DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n", - takenBkpt.address, notTakenBkpt.address); + takenBkpt, notTakenBkpt); - if (takenBkpt.address != 0) + if (takenBkpt != 0) clearTempBreakpoint(takenBkpt); - if (notTakenBkpt.address != 0) + if (notTakenBkpt != 0) clearTempBreakpoint(notTakenBkpt); } @@ -322,12 +285,12 @@ RemoteGDB::setSingleStep() } DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n", - takenBkpt.address, notTakenBkpt.address); + takenBkpt, notTakenBkpt); - setTempBreakpoint(notTakenBkpt, npc); + setTempBreakpoint(notTakenBkpt = npc); if (set_bt) - setTempBreakpoint(takenBkpt, bpc); + setTempBreakpoint(takenBkpt = bpc); } // Write bytes to kernel address space for debugger. @@ -344,81 +307,3 @@ RemoteGDB::write(Addr vaddr, size_t size, const char *data) } } - -PCEventQueue *RemoteGDB::getPcEventQueue() -{ - return &system->pcEventQueue; -} - - -RemoteGDB::HardBreakpoint::HardBreakpoint(RemoteGDB *_gdb, Addr pc) - : PCEvent(_gdb->getPcEventQueue(), "HardBreakpoint Event", pc), - gdb(_gdb), refcount(0) -{ - DPRINTF(GDBMisc, "creating hardware breakpoint at %#x\n", evpc); -} - -void -RemoteGDB::HardBreakpoint::process(ThreadContext *tc) -{ - DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc()); - - if (tc == gdb->context) - gdb->trap(ALPHA_KENTRY_INT); -} - -bool -RemoteGDB::insertSoftBreak(Addr addr, size_t len) -{ - if (len != sizeof(MachInst)) - panic("invalid length\n"); - - return insertHardBreak(addr, len); -} - -bool -RemoteGDB::removeSoftBreak(Addr addr, size_t len) -{ - if (len != sizeof(MachInst)) - panic("invalid length\n"); - - return removeHardBreak(addr, len); -} - -bool -RemoteGDB::insertHardBreak(Addr addr, size_t len) -{ - if (len != sizeof(MachInst)) - panic("invalid length\n"); - - DPRINTF(GDBMisc, "inserting hardware breakpoint at %#x\n", addr); - - HardBreakpoint *&bkpt = hardBreakMap[addr]; - if (bkpt == 0) - bkpt = new HardBreakpoint(this, addr); - - bkpt->refcount++; - - return true; -} - -bool -RemoteGDB::removeHardBreak(Addr addr, size_t len) -{ - if (len != sizeof(MachInst)) - panic("invalid length\n"); - - DPRINTF(GDBMisc, "removing hardware breakpoint at %#x\n", addr); - - break_iter_t i = hardBreakMap.find(addr); - if (i == hardBreakMap.end()) - return false; - - HardBreakpoint *hbp = (*i).second; - if (--hbp->refcount == 0) { - delete hbp; - hardBreakMap.erase(i); - } - - return true; -} diff --git a/src/arch/alpha/remote_gdb.hh b/src/arch/alpha/remote_gdb.hh index 1dd4ada38..7bef183c3 100644 --- a/src/arch/alpha/remote_gdb.hh +++ b/src/arch/alpha/remote_gdb.hh @@ -48,31 +48,12 @@ namespace AlphaISA { class RemoteGDB : public BaseRemoteGDB { - private: - friend void debugger(); - friend class GDBListener; - - protected: - class Event : public PollEvent - { - protected: - RemoteGDB *gdb; - - public: - Event(RemoteGDB *g, int fd, int e); - void process(int revent); - }; - - friend class Event; - Event *event; - protected: // Machine memory bool write(Addr addr, size_t size, const char *data); public: RemoteGDB(System *system, ThreadContext *context); - ~RemoteGDB(); bool acc(Addr addr, size_t len); @@ -83,47 +64,10 @@ namespace AlphaISA void clearSingleStep(); void setSingleStep(); - PCEventQueue *getPcEventQueue(); - - protected: - class HardBreakpoint : public PCEvent - { - private: - RemoteGDB *gdb; - - public: - int refcount; - - public: - HardBreakpoint(RemoteGDB *_gdb, Addr addr); - std::string name() { return gdb->name() + ".hwbkpt"; } - - virtual void process(ThreadContext *tc); - }; - friend class HardBreakpoint; - - typedef std::map break_map_t; - typedef break_map_t::iterator break_iter_t; - break_map_t hardBreakMap; - - bool insertSoftBreak(Addr addr, size_t len); - bool removeSoftBreak(Addr addr, size_t len); - bool insertHardBreak(Addr addr, size_t len); - bool removeHardBreak(Addr addr, size_t len); - protected: - struct TempBreakpoint { - Addr address; // set here - MachInst bkpt_inst; // saved instruction at bkpt - int init_count; // number of times to skip bkpt - int count; // current count - }; - - TempBreakpoint notTakenBkpt; - TempBreakpoint takenBkpt; - void clearTempBreakpoint(TempBreakpoint &bkpt); - void setTempBreakpoint(TempBreakpoint &bkpt, Addr addr); + Addr notTakenBkpt; + Addr takenBkpt; }; } diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc index 2e662af7f..5f9c532b8 100644 --- a/src/arch/sparc/remote_gdb.cc +++ b/src/arch/sparc/remote_gdb.cc @@ -124,7 +124,6 @@ #include "arch/vtophys.hh" #include "arch/sparc/remote_gdb.hh" #include "base/intmath.hh" -#include "base/kgdb.h" #include "base/remote_gdb.hh" #include "base/socket.hh" #include "base/trace.hh" @@ -138,30 +137,10 @@ using namespace std; using namespace TheISA; -RemoteGDB::Event::Event(RemoteGDB *g, int fd, int e) - : PollEvent(fd, e), gdb(g) -{} - -void -RemoteGDB::Event::process(int revent) -{ - if (revent & POLLIN) - gdb->trap(ALPHA_KENTRY_IF); - else if (revent & POLLNVAL) - gdb->detach(); -} - RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) - : BaseRemoteGDB(_system, c, KGDB_NUMREGS), - event(NULL) + : BaseRemoteGDB(_system, c, NumGDBRegs) {} -RemoteGDB::~RemoteGDB() -{ - if (event) - delete event; -} - /////////////////////////////////////////////////////////// // RemoteGDB::acc // @@ -170,6 +149,7 @@ RemoteGDB::~RemoteGDB() bool RemoteGDB::acc(Addr va, size_t len) { +#if 0 Addr last_va; va = TheISA::TruncPage(va); @@ -208,40 +188,10 @@ RemoteGDB::acc(Addr va, size_t len) } while (va < last_va); DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); +#endif return true; } -/////////////////////////////////////////////////////////// -// RemoteGDB::signal -// -// Translate a trap number into a Unix-compatible signal number. -// (GDB only understands Unix signal numbers.) -// -int -RemoteGDB::signal(int type) -{ - switch (type) { - case ALPHA_KENTRY_INT: - return (SIGTRAP); - - case ALPHA_KENTRY_UNA: - return (SIGBUS); - - case ALPHA_KENTRY_ARITH: - return (SIGFPE); - - case ALPHA_KENTRY_IF: - return (SIGILL); - - case ALPHA_KENTRY_MM: - return (SIGSEGV); - - default: - panic("unknown signal type"); - return 0; - } -} - /////////////////////////////////////////////////////////// // RemoteGDB::getregs // @@ -252,24 +202,14 @@ RemoteGDB::getregs() { memset(gdbregs.regs, 0, gdbregs.size); - gdbregs.regs[KGDB_REG_PC] = context->readPC(); - - // @todo: Currently this is very Alpha specific. - if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { - for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { - gdbregs.regs[i] = context->readIntReg(AlphaISA::reg_redir[i]); - } - } else { - for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { - gdbregs.regs[i] = context->readIntReg(i); - } - } - -#ifdef KGDB_FP_REGS - for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { - gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i); - } -#endif + gdbregs.regs[RegPc] = context->readPC(); + gdbregs.regs[RegNpc] = context->readNextPC(); + for(int x = RegG0; x <= RegI7; x++) + gdbregs.regs[x] = context->readIntReg(x - RegG0); + for(int x = RegF0; x <= RegF31; x++) + gdbregs.regs[x] = context->readFloatRegBits(x - RegF0); + gdbregs.regs[RegY] = context->readMiscReg(MISCREG_Y); + //XXX need to also load up Psr, Wim, Tbr, Fpsr, and Cpsr } /////////////////////////////////////////////////////////// @@ -281,48 +221,20 @@ RemoteGDB::getregs() void RemoteGDB::setregs() { - // @todo: Currently this is very Alpha specific. - if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { - for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { - context->setIntReg(AlphaISA::reg_redir[i], gdbregs.regs[i]); - } - } else { - for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { - context->setIntReg(i, gdbregs.regs[i]); - } - } - -#ifdef KGDB_FP_REGS - for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { - context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]); - } -#endif - context->setPC(gdbregs.regs[KGDB_REG_PC]); -} - -void -RemoteGDB::setTempBreakpoint(TempBreakpoint &bkpt, Addr addr) -{ - DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", addr); - - bkpt.address = addr; - insertHardBreak(addr, 4); -} - -void -RemoteGDB::clearTempBreakpoint(TempBreakpoint &bkpt) -{ - DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", - bkpt.address); - - - removeHardBreak(bkpt.address, 4); - bkpt.address = 0; + context->setPC(gdbregs.regs[RegPc]); + context->setNextPC(gdbregs.regs[RegNpc]); + for(int x = RegG0; x <= RegI7; x++) + context->setIntReg(x - RegG0, gdbregs.regs[x]); + for(int x = RegF0; x <= RegF31; x++) + context->setFloatRegBits(x - RegF0, gdbregs.regs[x]); + context->setMiscRegWithEffect(MISCREG_Y, gdbregs.regs[RegY]); + //XXX need to also set Psr, Wim, Tbr, Fpsr, and Cpsr } void RemoteGDB::clearSingleStep() { +#if 0 DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n", takenBkpt.address, notTakenBkpt.address); @@ -331,11 +243,13 @@ RemoteGDB::clearSingleStep() if (notTakenBkpt.address != 0) clearTempBreakpoint(notTakenBkpt); +#endif } void RemoteGDB::setSingleStep() { +#if 0 Addr pc = context->readPC(); Addr npc, bpc; bool set_bt = false; @@ -360,97 +274,5 @@ RemoteGDB::setSingleStep() if (set_bt) setTempBreakpoint(takenBkpt, bpc); -} - -// Write bytes to kernel address space for debugger. -bool -RemoteGDB::write(Addr vaddr, size_t size, const char *data) -{ - if (BaseRemoteGDB::write(vaddr, size, data)) { -#ifdef IMB - alpha_pal_imb(); #endif - return true; - } else { - return false; - } -} - - -PCEventQueue *RemoteGDB::getPcEventQueue() -{ - return &system->pcEventQueue; -} - - -RemoteGDB::HardBreakpoint::HardBreakpoint(RemoteGDB *_gdb, Addr pc) - : PCEvent(_gdb->getPcEventQueue(), "HardBreakpoint Event", pc), - gdb(_gdb), refcount(0) -{ - DPRINTF(GDBMisc, "creating hardware breakpoint at %#x\n", evpc); -} - -void -RemoteGDB::HardBreakpoint::process(ThreadContext *tc) -{ - DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc()); - - if (tc == gdb->context) - gdb->trap(ALPHA_KENTRY_INT); -} - -bool -RemoteGDB::insertSoftBreak(Addr addr, size_t len) -{ - if (len != sizeof(MachInst)) - panic("invalid length\n"); - - return insertHardBreak(addr, len); -} - -bool -RemoteGDB::removeSoftBreak(Addr addr, size_t len) -{ - if (len != sizeof(MachInst)) - panic("invalid length\n"); - - return removeHardBreak(addr, len); -} - -bool -RemoteGDB::insertHardBreak(Addr addr, size_t len) -{ - if (len != sizeof(MachInst)) - panic("invalid length\n"); - - DPRINTF(GDBMisc, "inserting hardware breakpoint at %#x\n", addr); - - HardBreakpoint *&bkpt = hardBreakMap[addr]; - if (bkpt == 0) - bkpt = new HardBreakpoint(this, addr); - - bkpt->refcount++; - - return true; -} - -bool -RemoteGDB::removeHardBreak(Addr addr, size_t len) -{ - if (len != sizeof(MachInst)) - panic("invalid length\n"); - - DPRINTF(GDBMisc, "removing hardware breakpoint at %#x\n", addr); - - break_iter_t i = hardBreakMap.find(addr); - if (i == hardBreakMap.end()) - return false; - - HardBreakpoint *hbp = (*i).second; - if (--hbp->refcount == 0) { - delete hbp; - hardBreakMap.erase(i); - } - - return true; } diff --git a/src/arch/sparc/remote_gdb.hh b/src/arch/sparc/remote_gdb.hh index 6ac4f296f..3ded1e218 100644 --- a/src/arch/sparc/remote_gdb.hh +++ b/src/arch/sparc/remote_gdb.hh @@ -46,34 +46,32 @@ namespace SparcISA { class RemoteGDB : public BaseRemoteGDB { - private: - friend void debugger(); - friend class GDBListener; - protected: - class Event : public PollEvent + enum RegisterConstants { - protected: - RemoteGDB *gdb; - - public: - Event(RemoteGDB *g, int fd, int e); - void process(int revent); + RegG0, RegG1, RegG2, RegG3, RegG4, RegG5, RegG6, RegG7, + RegO0, RegO1, RegO2, RegO3, RegO4, RegO5, RegO6, RegO7, + RegL0, RegL1, RegL2, RegL3, RegL4, RegL5, RegL6, RegL7, + RegI0, RegI1, RegI2, RegI3, RegI4, RegI5, RegI6, RegI7, + RegF0, RegF1, RegF2, RegF3, RegF4, RegF5, RegF6, RegF7, + RegF8, RegF9, RegF10, RegF11, RegF12, RegF13, RegF14, RegF15, + RegF16, RegF17, RegF18, RegF19, RegF20, RegF21, RegF22, RegF23, + RegF24, RegF25, RegF26, RegF27, RegF28, RegF29, RegF30, RegF31, + RegY, + RegPsr, + RegWim, + RegTbr, + RegPc, + RegNpc, + RegFpsr, + RegCpsr, + NumGDBRegs }; - friend class Event; - Event *event; - - protected: - // Machine memory - bool write(Addr addr, size_t size, const char *data); - public: RemoteGDB(System *system, ThreadContext *context); - ~RemoteGDB(); bool acc(Addr addr, size_t len); - int signal(int type); protected: void getregs(); @@ -82,47 +80,7 @@ namespace SparcISA void clearSingleStep(); void setSingleStep(); - PCEventQueue *getPcEventQueue(); - - protected: - class HardBreakpoint : public PCEvent - { - private: - RemoteGDB *gdb; - - public: - int refcount; - - public: - HardBreakpoint(RemoteGDB *_gdb, Addr addr); - std::string name() { return gdb->name() + ".hwbkpt"; } - - virtual void process(ThreadContext *tc); - }; - friend class HardBreakpoint; - - typedef std::map break_map_t; - typedef break_map_t::iterator break_iter_t; - break_map_t hardBreakMap; - - bool insertSoftBreak(Addr addr, size_t len); - bool removeSoftBreak(Addr addr, size_t len); - bool insertHardBreak(Addr addr, size_t len); - bool removeHardBreak(Addr addr, size_t len); - - protected: - struct TempBreakpoint { - Addr address; // set here - MachInst bkpt_inst; // saved instruction at bkpt - int init_count; // number of times to skip bkpt - int count; // current count - }; - - TempBreakpoint notTakenBkpt; - TempBreakpoint takenBkpt; - - void clearTempBreakpoint(TempBreakpoint &bkpt); - void setTempBreakpoint(TempBreakpoint &bkpt, Addr addr); + Addr singleStepBreaks[2]; }; } -- cgit v1.2.3 From bcd5099aace33750d38d4270ceb93c000ac2288e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:40:06 -0500 Subject: Added in alot of missing source files. --HG-- extra : convert_revision : 335b458d195a00dac3d04e92fe9df915e660538f --- src/arch/sparc/SConscript | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 5843058a4..281c166c0 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -54,8 +54,12 @@ base_sources = Split(''' # Full-system sources full_system_sources = Split(''' - vtophys.cc + arguments.cc + remote_gdb.cc + stacktrace.cc system.cc + tlb.cc + vtophys.cc ''') # Syscall emulation (non-full-system) sources -- cgit v1.2.3 From 0c9bcf209a2d169dbd37f576c2f3c6f74deda192 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:40:48 -0500 Subject: The normal spill and fill faults only need to behave specially in SE. --HG-- extra : convert_revision : 4d4b866699e3450b88418822fc198411ee3d831a --- src/arch/sparc/faults.hh | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 0c7106707..b25b7706e 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -548,7 +548,10 @@ class SpillNNormal : public EnumeratedFault FaultName name() {return _name;} FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} + //These need to be handled specially to enable spill traps in SE +#if !FULL_SYSTEM void invoke(ThreadContext * tc); +#endif }; class SpillNOther : public EnumeratedFault @@ -579,7 +582,10 @@ class FillNNormal : public EnumeratedFault FaultName name() {return _name;} FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} + //These need to be handled specially to enable fill traps in SE +#if !FULL_SYSTEM void invoke(ThreadContext * tc); +#endif }; class FillNOther : public EnumeratedFault -- cgit v1.2.3 From 74112dec522ace81203966b40d1e4b34773b01db Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:41:23 -0500 Subject: Added a stub implementation of fixFuncEventAddr to get past linker errors. --HG-- extra : convert_revision : 24ab1789496c5fae6c0992db2d521ea02354ee90 --- src/arch/sparc/system.hh | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh index 3c8c6327e..0b79eda38 100644 --- a/src/arch/sparc/system.hh +++ b/src/arch/sparc/system.hh @@ -111,8 +111,11 @@ class SparcSystem : public System return addFuncEvent(openbootSymtab, lbl); } - virtual Addr fixFuncEventAddr(Addr addr); - + virtual Addr fixFuncEventAddr(Addr addr) + { + //XXX This may eventually have to do something useful. + return addr; + } }; #endif -- cgit v1.2.3 From 7e422980e9f37603a4453567a319865b93be4527 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:43:33 -0500 Subject: Arguments class for SPARC. This is basically just a copy of Alpha's --HG-- extra : convert_revision : 9df68973c63d5ff256d6de485e8d918c454c8ff1 --- src/arch/sparc/arguments.cc | 71 +++++++++++++++++++++ src/arch/sparc/arguments.hh | 149 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+) create mode 100644 src/arch/sparc/arguments.cc create mode 100644 src/arch/sparc/arguments.hh (limited to 'src/arch') diff --git a/src/arch/sparc/arguments.cc b/src/arch/sparc/arguments.cc new file mode 100644 index 000000000..a0a31567e --- /dev/null +++ b/src/arch/sparc/arguments.cc @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#include "arch/sparc/arguments.hh" +#include "arch/sparc/vtophys.hh" +#include "cpu/thread_context.hh" +#include "mem/vport.hh" + +using namespace SparcISA; + +Arguments::Data::~Data() +{ + while (!data.empty()) { + delete [] data.front(); + data.pop_front(); + } +} + +char * +Arguments::Data::alloc(size_t size) +{ + char *buf = new char[size]; + data.push_back(buf); + return buf; +} + +uint64_t +Arguments::getArg(bool fp) +{ + //XXX This needs to be replaced with the sparc version + if (number < 6) { + if (fp) + return tc->readFloatRegBits(16 + number); + else + return tc->readIntReg(16 + number); + } else { + Addr sp = tc->readIntReg(30); + VirtualPort *vp = tc->getVirtPort(tc); + uint64_t arg = vp->read(sp + (number-6) * sizeof(uint64_t)); + tc->delVirtPort(vp); + return arg; + } +} + diff --git a/src/arch/sparc/arguments.hh b/src/arch/sparc/arguments.hh new file mode 100644 index 000000000..0d059a564 --- /dev/null +++ b/src/arch/sparc/arguments.hh @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#ifndef __ARCH_SPARC_ARGUMENTS_HH__ +#define __ARCH_SPARC_ARGUMENTS_HH__ + +#include + +#include "arch/sparc/vtophys.hh" +#include "base/refcnt.hh" +#include "sim/host.hh" + +class ThreadContext; + +namespace SparcISA { + +class Arguments +{ + protected: + ThreadContext *tc; + int number; + uint64_t getArg(bool fp = false); + + protected: + class Data : public RefCounted + { + public: + Data(){} + ~Data(); + + private: + std::list data; + + public: + char *alloc(size_t size); + }; + + RefCountingPtr data; + + public: + Arguments(ThreadContext *ctx, int n = 0) + : tc(ctx), number(n), data(NULL) + { assert(number >= 0); data = new Data;} + Arguments(const Arguments &args) + : tc(args.tc), number(args.number), data(args.data) {} + ~Arguments() {} + + ThreadContext *getThreadContext() const { return tc; } + + const Arguments &operator=(const Arguments &args) { + tc = args.tc; + number = args.number; + data = args.data; + return *this; + } + + Arguments &operator++() { + ++number; + assert(number >= 0); + return *this; + } + + Arguments operator++(int) { + Arguments args = *this; + ++number; + assert(number >= 0); + return args; + } + + Arguments &operator--() { + --number; + assert(number >= 0); + return *this; + } + + Arguments operator--(int) { + Arguments args = *this; + --number; + assert(number >= 0); + return args; + } + + const Arguments &operator+=(int index) { + number += index; + assert(number >= 0); + return *this; + } + + const Arguments &operator-=(int index) { + number -= index; + assert(number >= 0); + return *this; + } + + Arguments operator[](int index) { + return Arguments(tc, index); + } + + template + operator T() { + assert(sizeof(T) <= sizeof(uint64_t)); + T data = static_cast(getArg()); + return data; + } + + template + operator T *() { + T *buf = (T *)data->alloc(sizeof(T)); + CopyData(tc, buf, getArg(), sizeof(T)); + return buf; + } + + operator char *() { + char *buf = data->alloc(2048); + CopyStringOut(tc, buf, getArg(), 2048); + return buf; + } +}; + +}; // namespace AlphaISA + +#endif // __ARCH_ALPHA_ARGUMENTS_HH__ -- cgit v1.2.3 From 48415ad2985d5b9fcd671a009c0f00afbe3c0abf Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:44:22 -0500 Subject: A dummy implementation of stacktrace.cc to clear up linker errors. --HG-- extra : convert_revision : ea1e54a529ad7ae4a6564dd6fb47c31fb0573adf --- src/arch/sparc/stacktrace.cc | 371 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 371 insertions(+) create mode 100644 src/arch/sparc/stacktrace.cc (limited to 'src/arch') diff --git a/src/arch/sparc/stacktrace.cc b/src/arch/sparc/stacktrace.cc new file mode 100644 index 000000000..0985eb149 --- /dev/null +++ b/src/arch/sparc/stacktrace.cc @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#include + +#include "arch/sparc/isa_traits.hh" +#include "arch/sparc/stacktrace.hh" +#include "arch/sparc/vtophys.hh" +#include "base/bitfield.hh" +#include "base/trace.hh" +#include "cpu/base.hh" +#include "cpu/thread_context.hh" +#include "sim/system.hh" + +using namespace std; +using namespace SparcISA; + +ProcessInfo::ProcessInfo(ThreadContext *_tc) + : tc(_tc) +{ + Addr addr = 0; + + VirtualPort *vp; + + vp = tc->getVirtPort(); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) + panic("thread info not compiled into kernel\n"); + thread_info_size = vp->readGtoH(addr); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) + panic("thread info not compiled into kernel\n"); + task_struct_size = vp->readGtoH(addr); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) + panic("thread info not compiled into kernel\n"); + task_off = vp->readGtoH(addr); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) + panic("thread info not compiled into kernel\n"); + pid_off = vp->readGtoH(addr); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) + panic("thread info not compiled into kernel\n"); + name_off = vp->readGtoH(addr); + + tc->delVirtPort(vp); +} + +Addr +ProcessInfo::task(Addr ksp) const +{ + Addr base = ksp & ~0x3fff; + if (base == ULL(0xfffffc0000000000)) + return 0; + + Addr tsk; + + VirtualPort *vp; + + vp = tc->getVirtPort(); + tsk = vp->readGtoH(base + task_off); + tc->delVirtPort(vp); + + return tsk; +} + +int +ProcessInfo::pid(Addr ksp) const +{ + Addr task = this->task(ksp); + if (!task) + return -1; + + uint16_t pd; + + VirtualPort *vp; + + vp = tc->getVirtPort(); + pd = vp->readGtoH(task + pid_off); + tc->delVirtPort(vp); + + return pd; +} + +string +ProcessInfo::name(Addr ksp) const +{ + Addr task = this->task(ksp); + if (!task) + return "console"; + + char comm[256]; + CopyStringOut(tc, comm, task + name_off, sizeof(comm)); + if (!comm[0]) + return "startup"; + + return comm; +} + +StackTrace::StackTrace() + : tc(0), stack(64) +{ +} + +StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) + : tc(0), stack(64) +{ + trace(_tc, inst); +} + +StackTrace::~StackTrace() +{ +} + +void +StackTrace::trace(ThreadContext *_tc, bool is_call) +{ +#if 0 + tc = _tc; + + bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + + Addr pc = tc->readNextPC(); + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; + + if (usermode) { + stack.push_back(user); + return; + } + + if (!kernel) { + stack.push_back(console); + return; + } + + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + Addr ksp = tc->readIntReg(TheISA::StackPointerReg); + Addr bottom = ksp & ~0x3fff; + Addr addr; + + if (is_call) { + if (!symtab->findNearestAddr(pc, addr)) + panic("could not find address %#x", pc); + + stack.push_back(addr); + pc = tc->readPC(); + } + + Addr ra; + int size; + + while (ksp > bottom) { + if (!symtab->findNearestAddr(pc, addr)) + panic("could not find symbol for pc=%#x", pc); + assert(pc >= addr && "symbol botch: callpc < func"); + + stack.push_back(addr); + + if (isEntry(addr)) + return; + + if (decodePrologue(ksp, pc, addr, size, ra)) { + if (!ra) + return; + + if (size <= 0) { + stack.push_back(unknown); + return; + } + + pc = ra; + ksp += size; + } else { + stack.push_back(unknown); + return; + } + + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; + if (!kernel) + return; + + if (stack.size() >= 1000) + panic("unwinding too far"); + } + + panic("unwinding too far"); +#endif +} + +bool +StackTrace::isEntry(Addr addr) +{ +#if 0 + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) + return true; + + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) + return true; + + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) + return true; + + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) + return true; + + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) + return true; + + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) + return true; +#endif + return false; +} + +bool +StackTrace::decodeStack(MachInst inst, int &disp) +{ + // lda $sp, -disp($sp) + // + // Opcode<31:26> == 0x08 + // RA<25:21> == 30 + // RB<20:16> == 30 + // Disp<15:0> + const MachInst mem_mask = 0xffff0000; + const MachInst lda_pattern = 0x23de0000; + const MachInst lda_disp_mask = 0x0000ffff; + + // subq $sp, disp, $sp + // addq $sp, disp, $sp + // + // Opcode<31:26> == 0x10 + // RA<25:21> == 30 + // Lit<20:13> + // One<12> = 1 + // Func<11:5> == 0x20 (addq) + // Func<11:5> == 0x29 (subq) + // RC<4:0> == 30 + const MachInst intop_mask = 0xffe01fff; + const MachInst addq_pattern = 0x43c0141e; + const MachInst subq_pattern = 0x43c0153e; + const MachInst intop_disp_mask = 0x001fe000; + const int intop_disp_shift = 13; + + if ((inst & mem_mask) == lda_pattern) + disp = -sext<16>(inst & lda_disp_mask); + else if ((inst & intop_mask) == addq_pattern) + disp = -int((inst & intop_disp_mask) >> intop_disp_shift); + else if ((inst & intop_mask) == subq_pattern) + disp = int((inst & intop_disp_mask) >> intop_disp_shift); + else + return false; + + return true; +} + +bool +StackTrace::decodeSave(MachInst inst, int ®, int &disp) +{ + // lda $stq, disp($sp) + // + // Opcode<31:26> == 0x08 + // RA<25:21> == ? + // RB<20:16> == 30 + // Disp<15:0> + const MachInst stq_mask = 0xfc1f0000; + const MachInst stq_pattern = 0xb41e0000; + const MachInst stq_disp_mask = 0x0000ffff; + const MachInst reg_mask = 0x03e00000; + const int reg_shift = 21; + + if ((inst & stq_mask) == stq_pattern) { + reg = (inst & reg_mask) >> reg_shift; + disp = sext<16>(inst & stq_disp_mask); + } else { + return false; + } + + return true; +} + +/* + * Decode the function prologue for the function we're in, and note + * which registers are stored where, and how large the stack frame is. + */ +bool +StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, + int &size, Addr &ra) +{ + size = 0; + ra = 0; + + for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { + MachInst inst; + CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); + + int reg, disp; + if (decodeStack(inst, disp)) { + if (size) { + // panic("decoding frame size again"); + return true; + } + size += disp; + } else if (decodeSave(inst, reg, disp)) { + if (!ra && reg == ReturnAddressReg) { + CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); + if (!ra) { + // panic("no return address value pc=%#x\n", pc); + return false; + } + } + } + } + + return true; +} + +#if TRACING_ON +void +StackTrace::dump() +{ + StringWrap name(tc->getCpuPtr()->name()); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + + DPRINTFN("------ Stack ------\n"); + + string symbol; + for (int i = 0, size = stack.size(); i < size; ++i) { + Addr addr = stack[size - i - 1]; + if (addr == user) + symbol = "user"; + else if (addr == console) + symbol = "console"; + else if (addr == unknown) + symbol = "unknown"; + else + symtab->findSymbol(addr, symbol); + + DPRINTFN("%#x: %s\n", addr, symbol); + } +} +#endif -- cgit v1.2.3 From c693c6ba9f9d641344db8a2a505484f5f8aa2645 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 22:34:34 -0500 Subject: Put kernel_stats back into arch. --HG-- rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966 --- src/arch/SConscript | 1 + src/arch/alpha/SConscript | 2 + src/arch/alpha/ev5.cc | 2 +- src/arch/alpha/idle_event.cc | 45 +++++++++ src/arch/alpha/idle_event.hh | 47 +++++++++ src/arch/alpha/kernel_stats.cc | 211 +++++++++++++++++++++++++++++++++++++++++ src/arch/alpha/kernel_stats.hh | 96 +++++++++++++++++++ src/arch/alpha/linux/system.cc | 2 +- src/arch/alpha/linux/system.hh | 2 +- src/arch/sparc/kernel_stats.hh | 57 +++++++++++ 10 files changed, 462 insertions(+), 3 deletions(-) create mode 100644 src/arch/alpha/idle_event.cc create mode 100644 src/arch/alpha/idle_event.hh create mode 100644 src/arch/alpha/kernel_stats.cc create mode 100644 src/arch/alpha/kernel_stats.hh create mode 100644 src/arch/sparc/kernel_stats.hh (limited to 'src/arch') diff --git a/src/arch/SConscript b/src/arch/SConscript index 82a56d4eb..bbe3c4e3a 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -51,6 +51,7 @@ isa_switch_hdrs = Split(''' faults.hh interrupts.hh isa_traits.hh + kernel_stats.hh locked_mem.hh process.hh regfile.hh diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 2d733d73b..3947ec23a 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -56,7 +56,9 @@ full_system_sources = Split(''' tlb.cc arguments.cc ev5.cc + idle_event.cc ipr.cc + kernel_stats.cc osfpal.cc stacktrace.cc vtophys.cc diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 76574e2df..59f9d2fb5 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -31,6 +31,7 @@ #include "arch/alpha/faults.hh" #include "arch/alpha/isa_traits.hh" +#include "arch/alpha/kernel_stats.hh" #include "arch/alpha/osfpal.hh" #include "arch/alpha/tlb.hh" #include "arch/alpha/kgdb.h" @@ -40,7 +41,6 @@ #include "cpu/base.hh" #include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" -#include "kern/alpha/kernel_stats.hh" #include "sim/debug.hh" #include "sim/sim_exit.hh" diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc new file mode 100644 index 000000000..0f6806319 --- /dev/null +++ b/src/arch/alpha/idle_event.cc @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Lisa Hsu + * Nathan Binkert + */ + +#include "arch/alpha/idle_event.hh" +#include "arch/alpha/kernel_stats.hh" +#include "cpu/thread_context.hh" + +using namespace TheISA; + +void +IdleStartEvent::process(ThreadContext *tc) +{ + if (tc->getKernelStats()) + tc->getKernelStats()->setIdleProcess( + tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc); + remove(); +} diff --git a/src/arch/alpha/idle_event.hh b/src/arch/alpha/idle_event.hh new file mode 100644 index 000000000..97d5bdd6e --- /dev/null +++ b/src/arch/alpha/idle_event.hh @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Lisa Hsu + * Ali Saidi + */ + +#ifndef __KERN_ALPHA_IDLE_EVENT_HH__ +#define __KERN_ALPHA_IDLE_EVENT_HH__ + +#include "cpu/pc_event.hh" + +class IdleStartEvent : public PCEvent +{ + public: + IdleStartEvent(PCEventQueue *q, const std::string &desc, Addr addr) + : PCEvent(q, desc, addr) + {} + virtual void process(ThreadContext *tc); +}; + +#endif // __KERN_ALPHA_IDLE_EVENT_HH__ diff --git a/src/arch/alpha/kernel_stats.cc b/src/arch/alpha/kernel_stats.cc new file mode 100644 index 000000000..6fc3cb72f --- /dev/null +++ b/src/arch/alpha/kernel_stats.cc @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Lisa Hsu + * Nathan Binkert + */ + +#include +#include +#include + +#include "arch/alpha/kernel_stats.hh" +#include "arch/alpha/osfpal.hh" +#include "base/trace.hh" +#include "cpu/thread_context.hh" +#include "kern/tru64/tru64_syscalls.hh" +#include "sim/system.hh" + +using namespace std; +using namespace Stats; + +namespace AlphaISA { +namespace Kernel { + +const char *modestr[] = { "kernel", "user", "idle" }; + +Statistics::Statistics(System *system) + : ::Kernel::Statistics(system), + idleProcess((Addr)-1), themode(kernel), lastModeTick(0) +{ +} + +void +Statistics::regStats(const string &_name) +{ + ::Kernel::Statistics::regStats(_name); + + _callpal + .init(256) + .name(name() + ".callpal") + .desc("number of callpals executed") + .flags(total | pdf | nozero | nonan) + ; + + for (int i = 0; i < PAL::NumCodes; ++i) { + const char *str = PAL::name(i); + if (str) + _callpal.subname(i, str); + } + + _hwrei + .name(name() + ".inst.hwrei") + .desc("number of hwrei instructions executed") + ; + + _mode + .init(cpu_mode_num) + .name(name() + ".mode_switch") + .desc("number of protection mode switches") + ; + + for (int i = 0; i < cpu_mode_num; ++i) + _mode.subname(i, modestr[i]); + + _modeGood + .init(cpu_mode_num) + .name(name() + ".mode_good") + ; + + for (int i = 0; i < cpu_mode_num; ++i) + _modeGood.subname(i, modestr[i]); + + _modeFraction + .name(name() + ".mode_switch_good") + .desc("fraction of useful protection mode switches") + .flags(total) + ; + + for (int i = 0; i < cpu_mode_num; ++i) + _modeFraction.subname(i, modestr[i]); + + _modeFraction = _modeGood / _mode; + + _modeTicks + .init(cpu_mode_num) + .name(name() + ".mode_ticks") + .desc("number of ticks spent at the given mode") + .flags(pdf) + ; + for (int i = 0; i < cpu_mode_num; ++i) + _modeTicks.subname(i, modestr[i]); + + _swap_context + .name(name() + ".swap_context") + .desc("number of times the context was actually changed") + ; +} + +void +Statistics::setIdleProcess(Addr idlepcbb, ThreadContext *tc) +{ + assert(themode == kernel); + idleProcess = idlepcbb; + themode = idle; + changeMode(themode, tc); +} + +void +Statistics::changeMode(cpu_mode newmode, ThreadContext *tc) +{ + _mode[newmode]++; + + if (newmode == themode) + return; + + DPRINTF(Context, "old mode=%-8s new mode=%-8s\n", + modestr[themode], modestr[newmode]); + + _modeGood[newmode]++; + _modeTicks[themode] += curTick - lastModeTick; + + lastModeTick = curTick; + themode = newmode; +} + +void +Statistics::mode(cpu_mode newmode, ThreadContext *tc) +{ + Addr pcbb = tc->readMiscReg(AlphaISA::IPR_PALtemp23); + + if (newmode == kernel && pcbb == idleProcess) + newmode = idle; + + changeMode(newmode, tc); +} + +void +Statistics::context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc) +{ + assert(themode != user); + + _swap_context++; + changeMode(newpcbb == idleProcess ? idle : kernel, tc); +} + +void +Statistics::callpal(int code, ThreadContext *tc) +{ + if (!PAL::name(code)) + return; + + _callpal[code]++; + + switch (code) { + case PAL::callsys: { + int number = tc->readIntReg(0); + if (SystemCalls::validSyscallNumber(number)) { + int cvtnum = SystemCalls::convert(number); + _syscall[cvtnum]++; + } + } break; + } +} + +void +Statistics::serialize(ostream &os) +{ + ::Kernel::Statistics::serialize(os); + int exemode = themode; + SERIALIZE_SCALAR(exemode); + SERIALIZE_SCALAR(idleProcess); + SERIALIZE_SCALAR(lastModeTick); +} + +void +Statistics::unserialize(Checkpoint *cp, const string §ion) +{ + ::Kernel::Statistics::unserialize(cp, section); + int exemode; + UNSERIALIZE_SCALAR(exemode); + UNSERIALIZE_SCALAR(idleProcess); + UNSERIALIZE_SCALAR(lastModeTick); + themode = (cpu_mode)exemode; +} + +} /* end namespace AlphaISA::Kernel */ +} /* end namespace AlphaISA */ diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh new file mode 100644 index 000000000..7b8640ad7 --- /dev/null +++ b/src/arch/alpha/kernel_stats.hh @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Lisa Hsu + * Nathan Binkert + */ + +#ifndef __ARCH_ALPHA_KERNEL_STATS_HH__ +#define __ARCH_ALPHA_KERNEL_STATS_HH__ + +#include +#include +#include +#include + +#include "cpu/static_inst.hh" +#include "kern/kernel_stats.hh" + +class BaseCPU; +class ThreadContext; +class FnEvent; +// What does kernel stats expect is included? +class System; + +namespace AlphaISA { +namespace Kernel { + +enum cpu_mode { kernel, user, idle, cpu_mode_num }; +extern const char *modestr[]; + +class Statistics : public ::Kernel::Statistics +{ + protected: + Addr idleProcess; + cpu_mode themode; + Tick lastModeTick; + + void changeMode(cpu_mode newmode, ThreadContext *tc); + + private: + Stats::Vector<> _callpal; +// Stats::Vector<> _faults; + + Stats::Vector<> _mode; + Stats::Vector<> _modeGood; + Stats::Formula _modeFraction; + Stats::Vector<> _modeTicks; + + Stats::Scalar<> _swap_context; + + public: + Statistics(System *system); + + void regStats(const std::string &name); + + public: + void mode(cpu_mode newmode, ThreadContext *tc); + void context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc); + void callpal(int code, ThreadContext *tc); + void hwrei() { _hwrei++; } + + void setIdleProcess(Addr idle, ThreadContext *tc); + + public: + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); +}; + +} /* end namespace AlphaISA::Kernel */ +} /* end namespace AlphaISA */ + +#endif // __ARCH_ALPHA_KERNEL_STATS_HH__ diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index 00684edbb..9a452e10f 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -42,6 +42,7 @@ #include "arch/arguments.hh" #include "arch/vtophys.hh" +#include "arch/alpha/idle_event.hh" #include "arch/alpha/linux/system.hh" #include "arch/alpha/linux/threadinfo.hh" #include "arch/alpha/system.hh" @@ -49,7 +50,6 @@ #include "cpu/thread_context.hh" #include "cpu/base.hh" #include "dev/platform.hh" -#include "kern/alpha/idle_event.hh" #include "kern/linux/printk.hh" #include "kern/linux/events.hh" #include "mem/physical.hh" diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh index d4c92ac01..14396f8ab 100644 --- a/src/arch/alpha/linux/system.hh +++ b/src/arch/alpha/linux/system.hh @@ -38,8 +38,8 @@ class ThreadContext; class BreakPCEvent; class IdleStartEvent; +#include "arch/alpha/idle_event.hh" #include "arch/alpha/system.hh" -#include "kern/alpha/idle_event.hh" #include "kern/linux/events.hh" using namespace AlphaISA; diff --git a/src/arch/sparc/kernel_stats.hh b/src/arch/sparc/kernel_stats.hh new file mode 100644 index 000000000..c007c54c2 --- /dev/null +++ b/src/arch/sparc/kernel_stats.hh @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_SPARC_KERNEL_STATS_HH__ +#define __ARCH_SPARC_KERNEL_STATS_HH__ + +#include +#include +#include +#include + +#include "kern/kernel_stats.hh" + +namespace SparcISA { +namespace Kernel { + +enum cpu_mode { hypervisor, kernel, user, idle, cpu_mode_num }; +extern const char *modestr[]; + +class Statistics : public ::Kernel::Statistics +{ + public: + Statistics(System *system) : ::Kernel::Statistics(system) + {} +}; + +} /* end namespace AlphaISA::Kernel */ +} /* end namespace AlphaISA */ + +#endif // __ARCH_SPARC_KERNEL_STATS_HH__ -- cgit v1.2.3 From 1a5d5d0b561591a5775d4b5a253360b7cea9076e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 23:40:54 -0500 Subject: Force remote gdb code to use signal numbers and not ISA specific trap numbers. --HG-- extra : convert_revision : 4f45a4b48e3993ac6991db2afffbce2e666eab6c --- src/arch/alpha/kgdb.h | 11 ----------- src/arch/alpha/system.cc | 4 +++- 2 files changed, 3 insertions(+), 12 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/kgdb.h b/src/arch/alpha/kgdb.h index 104244d0b..912cf6d45 100644 --- a/src/arch/alpha/kgdb.h +++ b/src/arch/alpha/kgdb.h @@ -160,15 +160,4 @@ /* Too much? Must be large enough for register transfer. */ #define KGDB_BUFLEN 1024 -/* - * Kernel Entry Vectors. [OSF/1 PALcode Specific] - */ - -#define ALPHA_KENTRY_INT 0 -#define ALPHA_KENTRY_ARITH 1 -#define ALPHA_KENTRY_MM 2 -#define ALPHA_KENTRY_IF 3 -#define ALPHA_KENTRY_UNA 4 -#define ALPHA_KENTRY_SYS 5 - #endif /* __KGDB_H__ */ diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc index 710f6ef46..cd923948c 100644 --- a/src/arch/alpha/system.cc +++ b/src/arch/alpha/system.cc @@ -29,6 +29,8 @@ * Nathan Binkert */ +#include + #include "arch/alpha/ev5.hh" #include "arch/alpha/system.hh" #include "arch/alpha/remote_gdb.hh" @@ -196,7 +198,7 @@ AlphaSystem::setAlphaAccess(Addr access) bool AlphaSystem::breakpoint() { - return remoteGDB[0]->trap(ALPHA_KENTRY_INT); + return remoteGDB[0]->trap(SIGTRAP); } void -- cgit v1.2.3 From 746ceb93fdb13f74ea2e18f980d122f8bfb5cd0a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 00:32:04 -0500 Subject: Replaced getArg with a SPARC implementation. --HG-- extra : convert_revision : ba31171a81b6c46de2997de2701d35fcf8c614b7 --- src/arch/sparc/arguments.cc | 16 +++++++++------- src/arch/sparc/arguments.hh | 4 ++-- 2 files changed, 11 insertions(+), 9 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/arguments.cc b/src/arch/sparc/arguments.cc index a0a31567e..44adf4a15 100644 --- a/src/arch/sparc/arguments.cc +++ b/src/arch/sparc/arguments.cc @@ -54,16 +54,18 @@ Arguments::Data::alloc(size_t size) uint64_t Arguments::getArg(bool fp) { - //XXX This needs to be replaced with the sparc version + //The caller uses %o0-%05 for the first 6 arguments even if their floating + //point. Double precision floating point values take two registers/args. + //Quads, structs, and unions are passed as pointers. All arguments beyond + //the sixth are passed on the stack past the 16 word window save area, + //space for the struct/union return pointer, and space reserved for the + //first 6 arguments which the caller may use but doesn't have to. if (number < 6) { - if (fp) - return tc->readFloatRegBits(16 + number); - else - return tc->readIntReg(16 + number); + return tc->readIntReg(8 + number); } else { - Addr sp = tc->readIntReg(30); + Addr sp = tc->readIntReg(14); VirtualPort *vp = tc->getVirtPort(tc); - uint64_t arg = vp->read(sp + (number-6) * sizeof(uint64_t)); + uint64_t arg = vp->read(sp + 92 + (number-6) * sizeof(uint64_t)); tc->delVirtPort(vp); return arg; } diff --git a/src/arch/sparc/arguments.hh b/src/arch/sparc/arguments.hh index 0d059a564..8f925dd25 100644 --- a/src/arch/sparc/arguments.hh +++ b/src/arch/sparc/arguments.hh @@ -144,6 +144,6 @@ class Arguments } }; -}; // namespace AlphaISA +}; // namespace SparcISA -#endif // __ARCH_ALPHA_ARGUMENTS_HH__ +#endif // __ARCH_SPARC_ARGUMENTS_HH__ -- cgit v1.2.3 From 16a012e80da8beb2e147bf62ed0d054ed1c0d600 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 00:32:40 -0500 Subject: Stubs for SPARC's tlbs --HG-- extra : convert_revision : ba08da78693cc6f59f7358134f121f471910dbf6 --- src/arch/sparc/tlb.cc | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/arch/sparc/tlb.hh | 16 ++++++++++- 2 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 src/arch/sparc/tlb.cc (limited to 'src/arch') diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc new file mode 100644 index 000000000..0b1a2ff5f --- /dev/null +++ b/src/arch/sparc/tlb.cc @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2001-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + * Andrew Schultz + */ + +#include "arch/sparc/tlb.hh" +#include "sim/builder.hh" + +namespace SparcISA +{ + DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) + + BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) + + Param size; + + END_DECLARE_SIM_OBJECT_PARAMS(ITB) + + BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) + + INIT_PARAM_DFLT(size, "TLB size", 48) + + END_INIT_SIM_OBJECT_PARAMS(ITB) + + + CREATE_SIM_OBJECT(ITB) + { + return new ITB(getInstanceName(), size); + } + + REGISTER_SIM_OBJECT("SparcITB", ITB) + + BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) + + Param size; + + END_DECLARE_SIM_OBJECT_PARAMS(DTB) + + BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) + + INIT_PARAM_DFLT(size, "TLB size", 64) + + END_INIT_SIM_OBJECT_PARAMS(DTB) + + + CREATE_SIM_OBJECT(DTB) + { + return new DTB(getInstanceName(), size); + } + + REGISTER_SIM_OBJECT("SparcDTB", DTB) +} diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 0d42e2c97..0fdba6baf 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -31,19 +31,29 @@ #ifndef __ARCH_SPARC_TLB_HH__ #define __ARCH_SPARC_TLB_HH__ +#include "mem/request.hh" #include "sim/faults.hh" +#include "sim/sim_object.hh" class ThreadContext; namespace SparcISA { - class TLB + class TLB : public SimObject { + public: + TLB(const std::string &name, int size) : SimObject(name) + { + } }; class ITB : public TLB { public: + ITB(const std::string &name, int size) : TLB(name, size) + { + } + Fault translate(RequestPtr &req, ThreadContext *tc) const { return NoFault; @@ -53,6 +63,10 @@ namespace SparcISA class DTB : public TLB { public: + DTB(const std::string &name, int size) : TLB(name, size) + { + } + Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const { return NoFault; -- cgit v1.2.3 From f1a55570d305dd15d7bc9667453a0ca14bf16462 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 00:52:04 -0500 Subject: Put the ProcessInfo and StackTrace objects into the ISA namespaces. --HG-- extra : convert_revision : 1626703583f02a1c9823874290462c1b6bdb6c3c --- src/arch/alpha/stacktrace.cc | 518 +++++++++++++++++++++--------------------- src/arch/alpha/stacktrace.hh | 130 +++++------ src/arch/sparc/stacktrace.cc | 521 ++++++++++++++++++++++--------------------- src/arch/sparc/stacktrace.hh | 131 +++++------ 4 files changed, 655 insertions(+), 645 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc index d70a4d6dd..c4612e156 100644 --- a/src/arch/alpha/stacktrace.cc +++ b/src/arch/alpha/stacktrace.cc @@ -40,329 +40,331 @@ #include "sim/system.hh" using namespace std; -using namespace AlphaISA; -ProcessInfo::ProcessInfo(ThreadContext *_tc) - : tc(_tc) +namespace AlphaISA { - Addr addr = 0; + ProcessInfo::ProcessInfo(ThreadContext *_tc) + : tc(_tc) + { + Addr addr = 0; - VirtualPort *vp; + VirtualPort *vp; - vp = tc->getVirtPort(); + vp = tc->getVirtPort(); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) - panic("thread info not compiled into kernel\n"); - thread_info_size = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) + panic("thread info not compiled into kernel\n"); + thread_info_size = vp->readGtoH(addr); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) - panic("thread info not compiled into kernel\n"); - task_struct_size = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) + panic("thread info not compiled into kernel\n"); + task_struct_size = vp->readGtoH(addr); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) - panic("thread info not compiled into kernel\n"); - task_off = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) + panic("thread info not compiled into kernel\n"); + task_off = vp->readGtoH(addr); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) - panic("thread info not compiled into kernel\n"); - pid_off = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) + panic("thread info not compiled into kernel\n"); + pid_off = vp->readGtoH(addr); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) - panic("thread info not compiled into kernel\n"); - name_off = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) + panic("thread info not compiled into kernel\n"); + name_off = vp->readGtoH(addr); - tc->delVirtPort(vp); -} - -Addr -ProcessInfo::task(Addr ksp) const -{ - Addr base = ksp & ~0x3fff; - if (base == ULL(0xfffffc0000000000)) - return 0; + tc->delVirtPort(vp); + } - Addr tsk; + Addr + ProcessInfo::task(Addr ksp) const + { + Addr base = ksp & ~0x3fff; + if (base == ULL(0xfffffc0000000000)) + return 0; - VirtualPort *vp; + Addr tsk; - vp = tc->getVirtPort(); - tsk = vp->readGtoH(base + task_off); - tc->delVirtPort(vp); + VirtualPort *vp; - return tsk; -} + vp = tc->getVirtPort(); + tsk = vp->readGtoH(base + task_off); + tc->delVirtPort(vp); -int -ProcessInfo::pid(Addr ksp) const -{ - Addr task = this->task(ksp); - if (!task) - return -1; + return tsk; + } - uint16_t pd; + int + ProcessInfo::pid(Addr ksp) const + { + Addr task = this->task(ksp); + if (!task) + return -1; - VirtualPort *vp; + uint16_t pd; - vp = tc->getVirtPort(); - pd = vp->readGtoH(task + pid_off); - tc->delVirtPort(vp); + VirtualPort *vp; - return pd; -} + vp = tc->getVirtPort(); + pd = vp->readGtoH(task + pid_off); + tc->delVirtPort(vp); -string -ProcessInfo::name(Addr ksp) const -{ - Addr task = this->task(ksp); - if (!task) - return "console"; + return pd; + } - char comm[256]; - CopyStringOut(tc, comm, task + name_off, sizeof(comm)); - if (!comm[0]) - return "startup"; + string + ProcessInfo::name(Addr ksp) const + { + Addr task = this->task(ksp); + if (!task) + return "console"; - return comm; -} + char comm[256]; + CopyStringOut(tc, comm, task + name_off, sizeof(comm)); + if (!comm[0]) + return "startup"; -StackTrace::StackTrace() - : tc(0), stack(64) -{ -} + return comm; + } -StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) - : tc(0), stack(64) -{ - trace(_tc, inst); -} + StackTrace::StackTrace() + : tc(0), stack(64) + { + } -StackTrace::~StackTrace() -{ -} + StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) + : tc(0), stack(64) + { + trace(_tc, inst); + } -void -StackTrace::trace(ThreadContext *_tc, bool is_call) -{ - tc = _tc; + StackTrace::~StackTrace() + { + } - bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + void + StackTrace::trace(ThreadContext *_tc, bool is_call) + { + tc = _tc; - Addr pc = tc->readNextPC(); - bool kernel = tc->getSystemPtr()->kernelStart <= pc && - pc <= tc->getSystemPtr()->kernelEnd; + bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; - if (usermode) { - stack.push_back(user); - return; - } + Addr pc = tc->readNextPC(); + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; - if (!kernel) { - stack.push_back(console); - return; - } + if (usermode) { + stack.push_back(user); + return; + } - SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; - Addr ksp = tc->readIntReg(TheISA::StackPointerReg); - Addr bottom = ksp & ~0x3fff; - Addr addr; + if (!kernel) { + stack.push_back(console); + return; + } - if (is_call) { - if (!symtab->findNearestAddr(pc, addr)) - panic("could not find address %#x", pc); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + Addr ksp = tc->readIntReg(TheISA::StackPointerReg); + Addr bottom = ksp & ~0x3fff; + Addr addr; - stack.push_back(addr); - pc = tc->readPC(); - } + if (is_call) { + if (!symtab->findNearestAddr(pc, addr)) + panic("could not find address %#x", pc); - Addr ra; - int size; + stack.push_back(addr); + pc = tc->readPC(); + } - while (ksp > bottom) { - if (!symtab->findNearestAddr(pc, addr)) - panic("could not find symbol for pc=%#x", pc); - assert(pc >= addr && "symbol botch: callpc < func"); + Addr ra; + int size; - stack.push_back(addr); + while (ksp > bottom) { + if (!symtab->findNearestAddr(pc, addr)) + panic("could not find symbol for pc=%#x", pc); + assert(pc >= addr && "symbol botch: callpc < func"); - if (isEntry(addr)) - return; + stack.push_back(addr); - if (decodePrologue(ksp, pc, addr, size, ra)) { - if (!ra) + if (isEntry(addr)) return; - if (size <= 0) { + if (decodePrologue(ksp, pc, addr, size, ra)) { + if (!ra) + return; + + if (size <= 0) { + stack.push_back(unknown); + return; + } + + pc = ra; + ksp += size; + } else { stack.push_back(unknown); return; } - pc = ra; - ksp += size; - } else { - stack.push_back(unknown); - return; - } + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; + if (!kernel) + return; - bool kernel = tc->getSystemPtr()->kernelStart <= pc && - pc <= tc->getSystemPtr()->kernelEnd; - if (!kernel) - return; + if (stack.size() >= 1000) + panic("unwinding too far"); + } - if (stack.size() >= 1000) - panic("unwinding too far"); + panic("unwinding too far"); } - panic("unwinding too far"); -} + bool + StackTrace::isEntry(Addr addr) + { + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) + return true; -bool -StackTrace::isEntry(Addr addr) -{ - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) - return true; - - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) + return true; - return false; -} - -bool -StackTrace::decodeStack(MachInst inst, int &disp) -{ - // lda $sp, -disp($sp) - // - // Opcode<31:26> == 0x08 - // RA<25:21> == 30 - // RB<20:16> == 30 - // Disp<15:0> - const MachInst mem_mask = 0xffff0000; - const MachInst lda_pattern = 0x23de0000; - const MachInst lda_disp_mask = 0x0000ffff; - - // subq $sp, disp, $sp - // addq $sp, disp, $sp - // - // Opcode<31:26> == 0x10 - // RA<25:21> == 30 - // Lit<20:13> - // One<12> = 1 - // Func<11:5> == 0x20 (addq) - // Func<11:5> == 0x29 (subq) - // RC<4:0> == 30 - const MachInst intop_mask = 0xffe01fff; - const MachInst addq_pattern = 0x43c0141e; - const MachInst subq_pattern = 0x43c0153e; - const MachInst intop_disp_mask = 0x001fe000; - const int intop_disp_shift = 13; - - if ((inst & mem_mask) == lda_pattern) - disp = -sext<16>(inst & lda_disp_mask); - else if ((inst & intop_mask) == addq_pattern) - disp = -int((inst & intop_disp_mask) >> intop_disp_shift); - else if ((inst & intop_mask) == subq_pattern) - disp = int((inst & intop_disp_mask) >> intop_disp_shift); - else return false; + } - return true; -} + bool + StackTrace::decodeStack(MachInst inst, int &disp) + { + // lda $sp, -disp($sp) + // + // Opcode<31:26> == 0x08 + // RA<25:21> == 30 + // RB<20:16> == 30 + // Disp<15:0> + const MachInst mem_mask = 0xffff0000; + const MachInst lda_pattern = 0x23de0000; + const MachInst lda_disp_mask = 0x0000ffff; + + // subq $sp, disp, $sp + // addq $sp, disp, $sp + // + // Opcode<31:26> == 0x10 + // RA<25:21> == 30 + // Lit<20:13> + // One<12> = 1 + // Func<11:5> == 0x20 (addq) + // Func<11:5> == 0x29 (subq) + // RC<4:0> == 30 + const MachInst intop_mask = 0xffe01fff; + const MachInst addq_pattern = 0x43c0141e; + const MachInst subq_pattern = 0x43c0153e; + const MachInst intop_disp_mask = 0x001fe000; + const int intop_disp_shift = 13; + + if ((inst & mem_mask) == lda_pattern) + disp = -sext<16>(inst & lda_disp_mask); + else if ((inst & intop_mask) == addq_pattern) + disp = -int((inst & intop_disp_mask) >> intop_disp_shift); + else if ((inst & intop_mask) == subq_pattern) + disp = int((inst & intop_disp_mask) >> intop_disp_shift); + else + return false; -bool -StackTrace::decodeSave(MachInst inst, int ®, int &disp) -{ - // lda $stq, disp($sp) - // - // Opcode<31:26> == 0x08 - // RA<25:21> == ? - // RB<20:16> == 30 - // Disp<15:0> - const MachInst stq_mask = 0xfc1f0000; - const MachInst stq_pattern = 0xb41e0000; - const MachInst stq_disp_mask = 0x0000ffff; - const MachInst reg_mask = 0x03e00000; - const int reg_shift = 21; - - if ((inst & stq_mask) == stq_pattern) { - reg = (inst & reg_mask) >> reg_shift; - disp = sext<16>(inst & stq_disp_mask); - } else { - return false; + return true; } - return true; -} + bool + StackTrace::decodeSave(MachInst inst, int ®, int &disp) + { + // lda $stq, disp($sp) + // + // Opcode<31:26> == 0x08 + // RA<25:21> == ? + // RB<20:16> == 30 + // Disp<15:0> + const MachInst stq_mask = 0xfc1f0000; + const MachInst stq_pattern = 0xb41e0000; + const MachInst stq_disp_mask = 0x0000ffff; + const MachInst reg_mask = 0x03e00000; + const int reg_shift = 21; + + if ((inst & stq_mask) == stq_pattern) { + reg = (inst & reg_mask) >> reg_shift; + disp = sext<16>(inst & stq_disp_mask); + } else { + return false; + } -/* - * Decode the function prologue for the function we're in, and note - * which registers are stored where, and how large the stack frame is. - */ -bool -StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, - int &size, Addr &ra) -{ - size = 0; - ra = 0; - - for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { - MachInst inst; - CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); - - int reg, disp; - if (decodeStack(inst, disp)) { - if (size) { - // panic("decoding frame size again"); - return true; - } - size += disp; - } else if (decodeSave(inst, reg, disp)) { - if (!ra && reg == ReturnAddressReg) { - CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); - if (!ra) { - // panic("no return address value pc=%#x\n", pc); - return false; + return true; + } + + /* + * Decode the function prologue for the function we're in, and note + * which registers are stored where, and how large the stack frame is. + */ + bool + StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, + int &size, Addr &ra) + { + size = 0; + ra = 0; + + for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { + MachInst inst; + CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); + + int reg, disp; + if (decodeStack(inst, disp)) { + if (size) { + // panic("decoding frame size again"); + return true; + } + size += disp; + } else if (decodeSave(inst, reg, disp)) { + if (!ra && reg == ReturnAddressReg) { + CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); + if (!ra) { + // panic("no return address value pc=%#x\n", pc); + return false; + } } } } - } - return true; -} + return true; + } #if TRACING_ON -void -StackTrace::dump() -{ - StringWrap name(tc->getCpuPtr()->name()); - SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; - - DPRINTFN("------ Stack ------\n"); - - string symbol; - for (int i = 0, size = stack.size(); i < size; ++i) { - Addr addr = stack[size - i - 1]; - if (addr == user) - symbol = "user"; - else if (addr == console) - symbol = "console"; - else if (addr == unknown) - symbol = "unknown"; - else - symtab->findSymbol(addr, symbol); - - DPRINTFN("%#x: %s\n", addr, symbol); + void + StackTrace::dump() + { + StringWrap name(tc->getCpuPtr()->name()); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + + DPRINTFN("------ Stack ------\n"); + + string symbol; + for (int i = 0, size = stack.size(); i < size; ++i) { + Addr addr = stack[size - i - 1]; + if (addr == user) + symbol = "user"; + else if (addr == console) + symbol = "console"; + else if (addr == unknown) + symbol = "unknown"; + else + symtab->findSymbol(addr, symbol); + + DPRINTFN("%#x: %s\n", addr, symbol); + } } -} #endif +} diff --git a/src/arch/alpha/stacktrace.hh b/src/arch/alpha/stacktrace.hh index d12aee211..834abbc2f 100644 --- a/src/arch/alpha/stacktrace.hh +++ b/src/arch/alpha/stacktrace.hh @@ -35,87 +35,91 @@ #include "cpu/static_inst.hh" class ThreadContext; -class StackTrace; -class ProcessInfo +namespace AlphaISA { - private: - ThreadContext *tc; + class StackTrace; - int thread_info_size; - int task_struct_size; - int task_off; - int pid_off; - int name_off; + class ProcessInfo + { + private: + ThreadContext *tc; - public: - ProcessInfo(ThreadContext *_tc); + int thread_info_size; + int task_struct_size; + int task_off; + int pid_off; + int name_off; - Addr task(Addr ksp) const; - int pid(Addr ksp) const; - std::string name(Addr ksp) const; -}; + public: + ProcessInfo(ThreadContext *_tc); -class StackTrace -{ - protected: - typedef TheISA::MachInst MachInst; - private: - ThreadContext *tc; - std::vector stack; - - private: - bool isEntry(Addr addr); - bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra); - bool decodeSave(MachInst inst, int ®, int &disp); - bool decodeStack(MachInst inst, int &disp); - - void trace(ThreadContext *tc, bool is_call); - - public: - StackTrace(); - StackTrace(ThreadContext *tc, StaticInstPtr inst); - ~StackTrace(); - - void clear() + Addr task(Addr ksp) const; + int pid(Addr ksp) const; + std::string name(Addr ksp) const; + }; + + class StackTrace { - tc = 0; - stack.clear(); - } + protected: + typedef TheISA::MachInst MachInst; + private: + ThreadContext *tc; + std::vector stack; + + private: + bool isEntry(Addr addr); + bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra); + bool decodeSave(MachInst inst, int ®, int &disp); + bool decodeStack(MachInst inst, int &disp); + + void trace(ThreadContext *tc, bool is_call); - bool valid() const { return tc != NULL; } - bool trace(ThreadContext *tc, StaticInstPtr inst); + public: + StackTrace(); + StackTrace(ThreadContext *tc, StaticInstPtr inst); + ~StackTrace(); - public: - const std::vector &getstack() const { return stack; } + void clear() + { + tc = 0; + stack.clear(); + } - static const int user = 1; - static const int console = 2; - static const int unknown = 3; + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); + + public: + const std::vector &getstack() const { return stack; } + + static const int user = 1; + static const int console = 2; + static const int unknown = 3; #if TRACING_ON - private: - void dump(); + private: + void dump(); - public: - void dprintf() { if (DTRACE(Stack)) dump(); } + public: + void dprintf() { if (DTRACE(Stack)) dump(); } #else - public: - void dprintf() {} + public: + void dprintf() {} #endif -}; + }; -inline bool -StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) -{ - if (!inst->isCall() && !inst->isReturn()) - return false; + inline bool + StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) + { + if (!inst->isCall() && !inst->isReturn()) + return false; - if (valid()) - clear(); + if (valid()) + clear(); - trace(tc, !inst->isReturn()); - return true; + trace(tc, !inst->isReturn()); + return true; + } } #endif // __ARCH_ALPHA_STACKTRACE_HH__ diff --git a/src/arch/sparc/stacktrace.cc b/src/arch/sparc/stacktrace.cc index 0985eb149..2eb697bf2 100644 --- a/src/arch/sparc/stacktrace.cc +++ b/src/arch/sparc/stacktrace.cc @@ -40,332 +40,333 @@ #include "sim/system.hh" using namespace std; -using namespace SparcISA; - -ProcessInfo::ProcessInfo(ThreadContext *_tc) - : tc(_tc) +namespace SparcISA { - Addr addr = 0; + ProcessInfo::ProcessInfo(ThreadContext *_tc) + : tc(_tc) + { + Addr addr = 0; - VirtualPort *vp; + VirtualPort *vp; - vp = tc->getVirtPort(); + vp = tc->getVirtPort(); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) - panic("thread info not compiled into kernel\n"); - thread_info_size = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) + panic("thread info not compiled into kernel\n"); + thread_info_size = vp->readGtoH(addr); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) - panic("thread info not compiled into kernel\n"); - task_struct_size = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) + panic("thread info not compiled into kernel\n"); + task_struct_size = vp->readGtoH(addr); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) - panic("thread info not compiled into kernel\n"); - task_off = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) + panic("thread info not compiled into kernel\n"); + task_off = vp->readGtoH(addr); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) - panic("thread info not compiled into kernel\n"); - pid_off = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) + panic("thread info not compiled into kernel\n"); + pid_off = vp->readGtoH(addr); - if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) - panic("thread info not compiled into kernel\n"); - name_off = vp->readGtoH(addr); + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) + panic("thread info not compiled into kernel\n"); + name_off = vp->readGtoH(addr); - tc->delVirtPort(vp); -} + tc->delVirtPort(vp); + } -Addr -ProcessInfo::task(Addr ksp) const -{ - Addr base = ksp & ~0x3fff; - if (base == ULL(0xfffffc0000000000)) - return 0; + Addr + ProcessInfo::task(Addr ksp) const + { + Addr base = ksp & ~0x3fff; + if (base == ULL(0xfffffc0000000000)) + return 0; - Addr tsk; + Addr tsk; - VirtualPort *vp; + VirtualPort *vp; - vp = tc->getVirtPort(); - tsk = vp->readGtoH(base + task_off); - tc->delVirtPort(vp); + vp = tc->getVirtPort(); + tsk = vp->readGtoH(base + task_off); + tc->delVirtPort(vp); - return tsk; -} + return tsk; + } -int -ProcessInfo::pid(Addr ksp) const -{ - Addr task = this->task(ksp); - if (!task) - return -1; + int + ProcessInfo::pid(Addr ksp) const + { + Addr task = this->task(ksp); + if (!task) + return -1; - uint16_t pd; + uint16_t pd; - VirtualPort *vp; + VirtualPort *vp; - vp = tc->getVirtPort(); - pd = vp->readGtoH(task + pid_off); - tc->delVirtPort(vp); + vp = tc->getVirtPort(); + pd = vp->readGtoH(task + pid_off); + tc->delVirtPort(vp); - return pd; -} + return pd; + } -string -ProcessInfo::name(Addr ksp) const -{ - Addr task = this->task(ksp); - if (!task) - return "console"; + string + ProcessInfo::name(Addr ksp) const + { + Addr task = this->task(ksp); + if (!task) + return "console"; - char comm[256]; - CopyStringOut(tc, comm, task + name_off, sizeof(comm)); - if (!comm[0]) - return "startup"; + char comm[256]; + CopyStringOut(tc, comm, task + name_off, sizeof(comm)); + if (!comm[0]) + return "startup"; - return comm; -} + return comm; + } -StackTrace::StackTrace() - : tc(0), stack(64) -{ -} + StackTrace::StackTrace() + : tc(0), stack(64) + { + } -StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) - : tc(0), stack(64) -{ - trace(_tc, inst); -} + StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) + : tc(0), stack(64) + { + trace(_tc, inst); + } -StackTrace::~StackTrace() -{ -} + StackTrace::~StackTrace() + { + } -void -StackTrace::trace(ThreadContext *_tc, bool is_call) -{ + void + StackTrace::trace(ThreadContext *_tc, bool is_call) + { #if 0 - tc = _tc; + tc = _tc; - bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; - Addr pc = tc->readNextPC(); - bool kernel = tc->getSystemPtr()->kernelStart <= pc && - pc <= tc->getSystemPtr()->kernelEnd; + Addr pc = tc->readNextPC(); + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; - if (usermode) { - stack.push_back(user); - return; - } + if (usermode) { + stack.push_back(user); + return; + } - if (!kernel) { - stack.push_back(console); - return; - } + if (!kernel) { + stack.push_back(console); + return; + } - SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; - Addr ksp = tc->readIntReg(TheISA::StackPointerReg); - Addr bottom = ksp & ~0x3fff; - Addr addr; + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + Addr ksp = tc->readIntReg(TheISA::StackPointerReg); + Addr bottom = ksp & ~0x3fff; + Addr addr; - if (is_call) { - if (!symtab->findNearestAddr(pc, addr)) - panic("could not find address %#x", pc); + if (is_call) { + if (!symtab->findNearestAddr(pc, addr)) + panic("could not find address %#x", pc); - stack.push_back(addr); - pc = tc->readPC(); - } + stack.push_back(addr); + pc = tc->readPC(); + } - Addr ra; - int size; + Addr ra; + int size; - while (ksp > bottom) { - if (!symtab->findNearestAddr(pc, addr)) - panic("could not find symbol for pc=%#x", pc); - assert(pc >= addr && "symbol botch: callpc < func"); + while (ksp > bottom) { + if (!symtab->findNearestAddr(pc, addr)) + panic("could not find symbol for pc=%#x", pc); + assert(pc >= addr && "symbol botch: callpc < func"); - stack.push_back(addr); + stack.push_back(addr); - if (isEntry(addr)) - return; - - if (decodePrologue(ksp, pc, addr, size, ra)) { - if (!ra) + if (isEntry(addr)) return; - if (size <= 0) { + if (decodePrologue(ksp, pc, addr, size, ra)) { + if (!ra) + return; + + if (size <= 0) { + stack.push_back(unknown); + return; + } + + pc = ra; + ksp += size; + } else { stack.push_back(unknown); return; } - pc = ra; - ksp += size; - } else { - stack.push_back(unknown); - return; - } - - bool kernel = tc->getSystemPtr()->kernelStart <= pc && - pc <= tc->getSystemPtr()->kernelEnd; - if (!kernel) - return; + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; + if (!kernel) + return; - if (stack.size() >= 1000) - panic("unwinding too far"); - } + if (stack.size() >= 1000) + panic("unwinding too far"); + } - panic("unwinding too far"); + panic("unwinding too far"); #endif -} + } -bool -StackTrace::isEntry(Addr addr) -{ + bool + StackTrace::isEntry(Addr addr) + { #if 0 - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) + return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) - return true; + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) + return true; #endif - return false; -} - -bool -StackTrace::decodeStack(MachInst inst, int &disp) -{ - // lda $sp, -disp($sp) - // - // Opcode<31:26> == 0x08 - // RA<25:21> == 30 - // RB<20:16> == 30 - // Disp<15:0> - const MachInst mem_mask = 0xffff0000; - const MachInst lda_pattern = 0x23de0000; - const MachInst lda_disp_mask = 0x0000ffff; - - // subq $sp, disp, $sp - // addq $sp, disp, $sp - // - // Opcode<31:26> == 0x10 - // RA<25:21> == 30 - // Lit<20:13> - // One<12> = 1 - // Func<11:5> == 0x20 (addq) - // Func<11:5> == 0x29 (subq) - // RC<4:0> == 30 - const MachInst intop_mask = 0xffe01fff; - const MachInst addq_pattern = 0x43c0141e; - const MachInst subq_pattern = 0x43c0153e; - const MachInst intop_disp_mask = 0x001fe000; - const int intop_disp_shift = 13; - - if ((inst & mem_mask) == lda_pattern) - disp = -sext<16>(inst & lda_disp_mask); - else if ((inst & intop_mask) == addq_pattern) - disp = -int((inst & intop_disp_mask) >> intop_disp_shift); - else if ((inst & intop_mask) == subq_pattern) - disp = int((inst & intop_disp_mask) >> intop_disp_shift); - else return false; + } - return true; -} + bool + StackTrace::decodeStack(MachInst inst, int &disp) + { + // lda $sp, -disp($sp) + // + // Opcode<31:26> == 0x08 + // RA<25:21> == 30 + // RB<20:16> == 30 + // Disp<15:0> + const MachInst mem_mask = 0xffff0000; + const MachInst lda_pattern = 0x23de0000; + const MachInst lda_disp_mask = 0x0000ffff; + + // subq $sp, disp, $sp + // addq $sp, disp, $sp + // + // Opcode<31:26> == 0x10 + // RA<25:21> == 30 + // Lit<20:13> + // One<12> = 1 + // Func<11:5> == 0x20 (addq) + // Func<11:5> == 0x29 (subq) + // RC<4:0> == 30 + const MachInst intop_mask = 0xffe01fff; + const MachInst addq_pattern = 0x43c0141e; + const MachInst subq_pattern = 0x43c0153e; + const MachInst intop_disp_mask = 0x001fe000; + const int intop_disp_shift = 13; + + if ((inst & mem_mask) == lda_pattern) + disp = -sext<16>(inst & lda_disp_mask); + else if ((inst & intop_mask) == addq_pattern) + disp = -int((inst & intop_disp_mask) >> intop_disp_shift); + else if ((inst & intop_mask) == subq_pattern) + disp = int((inst & intop_disp_mask) >> intop_disp_shift); + else + return false; -bool -StackTrace::decodeSave(MachInst inst, int ®, int &disp) -{ - // lda $stq, disp($sp) - // - // Opcode<31:26> == 0x08 - // RA<25:21> == ? - // RB<20:16> == 30 - // Disp<15:0> - const MachInst stq_mask = 0xfc1f0000; - const MachInst stq_pattern = 0xb41e0000; - const MachInst stq_disp_mask = 0x0000ffff; - const MachInst reg_mask = 0x03e00000; - const int reg_shift = 21; - - if ((inst & stq_mask) == stq_pattern) { - reg = (inst & reg_mask) >> reg_shift; - disp = sext<16>(inst & stq_disp_mask); - } else { - return false; + return true; } - return true; -} + bool + StackTrace::decodeSave(MachInst inst, int ®, int &disp) + { + // lda $stq, disp($sp) + // + // Opcode<31:26> == 0x08 + // RA<25:21> == ? + // RB<20:16> == 30 + // Disp<15:0> + const MachInst stq_mask = 0xfc1f0000; + const MachInst stq_pattern = 0xb41e0000; + const MachInst stq_disp_mask = 0x0000ffff; + const MachInst reg_mask = 0x03e00000; + const int reg_shift = 21; + + if ((inst & stq_mask) == stq_pattern) { + reg = (inst & reg_mask) >> reg_shift; + disp = sext<16>(inst & stq_disp_mask); + } else { + return false; + } -/* - * Decode the function prologue for the function we're in, and note - * which registers are stored where, and how large the stack frame is. - */ -bool -StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, - int &size, Addr &ra) -{ - size = 0; - ra = 0; - - for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { - MachInst inst; - CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); - - int reg, disp; - if (decodeStack(inst, disp)) { - if (size) { - // panic("decoding frame size again"); - return true; - } - size += disp; - } else if (decodeSave(inst, reg, disp)) { - if (!ra && reg == ReturnAddressReg) { - CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); - if (!ra) { - // panic("no return address value pc=%#x\n", pc); - return false; + return true; + } + + /* + * Decode the function prologue for the function we're in, and note + * which registers are stored where, and how large the stack frame is. + */ + bool + StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, + int &size, Addr &ra) + { + size = 0; + ra = 0; + + for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { + MachInst inst; + CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); + + int reg, disp; + if (decodeStack(inst, disp)) { + if (size) { + // panic("decoding frame size again"); + return true; + } + size += disp; + } else if (decodeSave(inst, reg, disp)) { + if (!ra && reg == ReturnAddressReg) { + CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); + if (!ra) { + // panic("no return address value pc=%#x\n", pc); + return false; + } } } } - } - return true; -} + return true; + } #if TRACING_ON -void -StackTrace::dump() -{ - StringWrap name(tc->getCpuPtr()->name()); - SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; - - DPRINTFN("------ Stack ------\n"); - - string symbol; - for (int i = 0, size = stack.size(); i < size; ++i) { - Addr addr = stack[size - i - 1]; - if (addr == user) - symbol = "user"; - else if (addr == console) - symbol = "console"; - else if (addr == unknown) - symbol = "unknown"; - else - symtab->findSymbol(addr, symbol); - - DPRINTFN("%#x: %s\n", addr, symbol); + void + StackTrace::dump() + { + StringWrap name(tc->getCpuPtr()->name()); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + + DPRINTFN("------ Stack ------\n"); + + string symbol; + for (int i = 0, size = stack.size(); i < size; ++i) { + Addr addr = stack[size - i - 1]; + if (addr == user) + symbol = "user"; + else if (addr == console) + symbol = "console"; + else if (addr == unknown) + symbol = "unknown"; + else + symtab->findSymbol(addr, symbol); + + DPRINTFN("%#x: %s\n", addr, symbol); + } } -} #endif +} diff --git a/src/arch/sparc/stacktrace.hh b/src/arch/sparc/stacktrace.hh index 54d3d17be..4bc5d779b 100644 --- a/src/arch/sparc/stacktrace.hh +++ b/src/arch/sparc/stacktrace.hh @@ -35,87 +35,90 @@ #include "cpu/static_inst.hh" class ThreadContext; -class StackTrace; - -class ProcessInfo +namespace SparcISA { - private: - ThreadContext *tc; + class StackTrace; - int thread_info_size; - int task_struct_size; - int task_off; - int pid_off; - int name_off; + class ProcessInfo + { + private: + ThreadContext *tc; - public: - ProcessInfo(ThreadContext *_tc); + int thread_info_size; + int task_struct_size; + int task_off; + int pid_off; + int name_off; - Addr task(Addr ksp) const; - int pid(Addr ksp) const; - std::string name(Addr ksp) const; -}; + public: + ProcessInfo(ThreadContext *_tc); -class StackTrace -{ - protected: - typedef TheISA::MachInst MachInst; - private: - ThreadContext *tc; - std::vector stack; - - private: - bool isEntry(Addr addr); - bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra); - bool decodeSave(MachInst inst, int ®, int &disp); - bool decodeStack(MachInst inst, int &disp); - - void trace(ThreadContext *tc, bool is_call); - - public: - StackTrace(); - StackTrace(ThreadContext *tc, StaticInstPtr inst); - ~StackTrace(); - - void clear() + Addr task(Addr ksp) const; + int pid(Addr ksp) const; + std::string name(Addr ksp) const; + }; + + class StackTrace { - tc = 0; - stack.clear(); - } + protected: + typedef TheISA::MachInst MachInst; + private: + ThreadContext *tc; + std::vector stack; + + private: + bool isEntry(Addr addr); + bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra); + bool decodeSave(MachInst inst, int ®, int &disp); + bool decodeStack(MachInst inst, int &disp); - bool valid() const { return tc != NULL; } - bool trace(ThreadContext *tc, StaticInstPtr inst); + void trace(ThreadContext *tc, bool is_call); - public: - const std::vector &getstack() const { return stack; } + public: + StackTrace(); + StackTrace(ThreadContext *tc, StaticInstPtr inst); + ~StackTrace(); - static const int user = 1; - static const int console = 2; - static const int unknown = 3; + void clear() + { + tc = 0; + stack.clear(); + } + + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); + + public: + const std::vector &getstack() const { return stack; } + + static const int user = 1; + static const int console = 2; + static const int unknown = 3; #if TRACING_ON - private: - void dump(); + private: + void dump(); - public: - void dprintf() { if (DTRACE(Stack)) dump(); } + public: + void dprintf() { if (DTRACE(Stack)) dump(); } #else - public: - void dprintf() {} + public: + void dprintf() {} #endif -}; + }; -inline bool -StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) -{ - if (!inst->isCall() && !inst->isReturn()) - return false; + inline bool + StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) + { + if (!inst->isCall() && !inst->isReturn()) + return false; - if (valid()) - clear(); + if (valid()) + clear(); - trace(tc, !inst->isReturn()); - return true; + trace(tc, !inst->isReturn()); + return true; + } } #endif // __ARCH_SPARC_STACKTRACE_HH__ -- cgit v1.2.3 From 8cb7ac090059db62f869f726ffef6f93c0e49beb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 02:13:47 -0500 Subject: Changed the getReg and setReg functions so that they work like netbsd. Apparently, gdb expects to do single stepping on its own, so those functions panic for SPARC. acc still needs to be implemented. --HG-- extra : convert_revision : c6e98e37b8ab3d6f8d6b3cd2c961faa65b08a179 --- src/arch/sparc/remote_gdb.cc | 97 +++++--------------------------------------- src/arch/sparc/remote_gdb.hh | 27 ++++-------- 2 files changed, 20 insertions(+), 104 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc index 5f9c532b8..c76f8b820 100644 --- a/src/arch/sparc/remote_gdb.cc +++ b/src/arch/sparc/remote_gdb.cc @@ -149,46 +149,9 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) bool RemoteGDB::acc(Addr va, size_t len) { -#if 0 - Addr last_va; - - va = TheISA::TruncPage(va); - last_va = TheISA::RoundPage(va + len); - - do { - if (TheISA::IsK0Seg(va)) { - if (va < (TheISA::K0SegBase + pmem->size())) { - DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= " - "%#x < K0SEG + size\n", va); - return true; - } else { - DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n", - va); - return false; - } - } - - /** - * This code says that all accesses to palcode (instruction and data) - * are valid since there isn't a va->pa mapping because palcode is - * accessed physically. At some point this should probably be cleaned up - * but there is no easy way to do it. - */ - - if (AlphaISA::PcPAL(va) || va < 0x10000) - return true; - - Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20); - TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va); - if (!pte.valid()) { - DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); - return false; - } - va += TheISA::PageBytes; - } while (va < last_va); - - DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); -#endif + //@Todo In NetBSD, this function checks if all addresses + //from va to va + len have valid page mape entries. Not + //sure how this will work for other OSes or in general. return true; } @@ -204,12 +167,11 @@ RemoteGDB::getregs() gdbregs.regs[RegPc] = context->readPC(); gdbregs.regs[RegNpc] = context->readNextPC(); - for(int x = RegG0; x <= RegI7; x++) + for(int x = RegG0; x <= RegI0 + 7; x++) gdbregs.regs[x] = context->readIntReg(x - RegG0); - for(int x = RegF0; x <= RegF31; x++) - gdbregs.regs[x] = context->readFloatRegBits(x - RegF0); - gdbregs.regs[RegY] = context->readMiscReg(MISCREG_Y); - //XXX need to also load up Psr, Wim, Tbr, Fpsr, and Cpsr + //Floating point registers are left at 0 in netbsd + //All registers other than the pc, npc and int regs + //are ignored as well. } /////////////////////////////////////////////////////////// @@ -223,56 +185,19 @@ RemoteGDB::setregs() { context->setPC(gdbregs.regs[RegPc]); context->setNextPC(gdbregs.regs[RegNpc]); - for(int x = RegG0; x <= RegI7; x++) + for(int x = RegG0; x <= RegI0 + 7; x++) context->setIntReg(x - RegG0, gdbregs.regs[x]); - for(int x = RegF0; x <= RegF31; x++) - context->setFloatRegBits(x - RegF0, gdbregs.regs[x]); - context->setMiscRegWithEffect(MISCREG_Y, gdbregs.regs[RegY]); - //XXX need to also set Psr, Wim, Tbr, Fpsr, and Cpsr + //Only the integer registers, pc and npc are set in netbsd } void RemoteGDB::clearSingleStep() { -#if 0 - DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n", - takenBkpt.address, notTakenBkpt.address); - - if (takenBkpt.address != 0) - clearTempBreakpoint(takenBkpt); - - if (notTakenBkpt.address != 0) - clearTempBreakpoint(notTakenBkpt); -#endif + panic("SPARC does not support hardware single stepping\n"); } void RemoteGDB::setSingleStep() { -#if 0 - Addr pc = context->readPC(); - Addr npc, bpc; - bool set_bt = false; - - npc = pc + sizeof(MachInst); - - // User was stopped at pc, e.g. the instruction at pc was not - // executed. - MachInst inst = read(pc); - StaticInstPtr si(inst); - if (si->hasBranchTarget(pc, context, bpc)) { - // Don't bother setting a breakpoint on the taken branch if it - // is the same as the next pc - if (bpc != npc) - set_bt = true; - } - - DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n", - takenBkpt.address, notTakenBkpt.address); - - setTempBreakpoint(notTakenBkpt, npc); - - if (set_bt) - setTempBreakpoint(takenBkpt, bpc); -#endif + panic("SPARC does not support hardware single stepping\n"); } diff --git a/src/arch/sparc/remote_gdb.hh b/src/arch/sparc/remote_gdb.hh index 3ded1e218..e4b66b783 100644 --- a/src/arch/sparc/remote_gdb.hh +++ b/src/arch/sparc/remote_gdb.hh @@ -49,22 +49,15 @@ namespace SparcISA protected: enum RegisterConstants { - RegG0, RegG1, RegG2, RegG3, RegG4, RegG5, RegG6, RegG7, - RegO0, RegO1, RegO2, RegO3, RegO4, RegO5, RegO6, RegO7, - RegL0, RegL1, RegL2, RegL3, RegL4, RegL5, RegL6, RegL7, - RegI0, RegI1, RegI2, RegI3, RegI4, RegI5, RegI6, RegI7, - RegF0, RegF1, RegF2, RegF3, RegF4, RegF5, RegF6, RegF7, - RegF8, RegF9, RegF10, RegF11, RegF12, RegF13, RegF14, RegF15, - RegF16, RegF17, RegF18, RegF19, RegF20, RegF21, RegF22, RegF23, - RegF24, RegF25, RegF26, RegF27, RegF28, RegF29, RegF30, RegF31, - RegY, - RegPsr, - RegWim, - RegTbr, - RegPc, - RegNpc, - RegFpsr, - RegCpsr, + RegG0 = 0, RegO0 = 8, RegL0 = 16, RegI0 = 24, + RegF0 = 32, RegF32 = 64, + RegPc = 80, RegNpc, RegCcr, RegFsr, RegFprs, RegY, RegAsi, + RegVer, RegTick, RegPil, RegPstate, + RegTstate, RegTba, RegTl, RegTt, RegTpc, RegTnpc, RegWstate, + RegCwp, RegCansave, RegCanrestore, RegCleanwin, RegOtherwin, + RegAsr16 = 103, + RegIcc = 119, RegXcc, + RegFcc0 = 121, NumGDBRegs }; @@ -79,8 +72,6 @@ namespace SparcISA void clearSingleStep(); void setSingleStep(); - - Addr singleStepBreaks[2]; }; } -- cgit v1.2.3 From f0c4d3664930f28229c7e336c4d4372b2e1d4c21 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 04:18:15 -0500 Subject: The new global level is computed with min, not max. --HG-- extra : convert_revision : 6339c82d3655694445c3eb43e467b9aa6b4c8224 --- src/arch/sparc/faults.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index da7fc730d..1a44d34cf 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -291,9 +291,9 @@ void doNormalFault(ThreadContext *tc, TrapType tt) //Update the global register level if(1/*We're delivering the trap in priveleged mode*/) - tc->setMiscReg(MISCREG_GL, max(GL+1, MaxGL)); + tc->setMiscReg(MISCREG_GL, min(GL+1, MaxGL)); else - tc->setMiscReg(MISCREG_GL, max(GL+1, MaxPGL)); + tc->setMiscReg(MISCREG_GL, min(GL+1, MaxPGL)); //PSTATE.mm is unchanged //PSTATE.pef = whether or not an fpu is present -- cgit v1.2.3 From 635df9ba1753915002d10611308cba98527929d3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 08:12:19 -0500 Subject: Major clean up of the fault code. --HG-- extra : convert_revision : eb7e016a127417cbb0e1e2c733b17f82469c2f24 --- src/arch/sparc/faults.cc | 281 +++++++++--------------- src/arch/sparc/faults.hh | 539 +++++++---------------------------------------- 2 files changed, 180 insertions(+), 640 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 2c8da44c5..169ad7986 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -48,192 +48,119 @@ using namespace std; namespace SparcISA { -FaultName InternalProcessorError::_name = "intprocerr"; -TrapType InternalProcessorError::_trapType = 0x029; -FaultPriority InternalProcessorError::_priority = 4; -FaultStat InternalProcessorError::_count; - -FaultName MemAddressNotAligned::_name = "unalign"; -TrapType MemAddressNotAligned::_trapType = 0x034; -FaultPriority MemAddressNotAligned::_priority = 10; -FaultStat MemAddressNotAligned::_count; - -FaultName PowerOnReset::_name = "pow_reset"; -TrapType PowerOnReset::_trapType = 0x001; -FaultPriority PowerOnReset::_priority = 0; -FaultStat PowerOnReset::_count; - -FaultName WatchDogReset::_name = "watch_dog_reset"; -TrapType WatchDogReset::_trapType = 0x002; -FaultPriority WatchDogReset::_priority = 1; -FaultStat WatchDogReset::_count; - -FaultName ExternallyInitiatedReset::_name = "extern_reset"; -TrapType ExternallyInitiatedReset::_trapType = 0x003; -FaultPriority ExternallyInitiatedReset::_priority = 1; -FaultStat ExternallyInitiatedReset::_count; - -FaultName SoftwareInitiatedReset::_name = "software_reset"; -TrapType SoftwareInitiatedReset::_trapType = 0x004; -FaultPriority SoftwareInitiatedReset::_priority = 1; -FaultStat SoftwareInitiatedReset::_count; - -FaultName REDStateException::_name = "red_counte"; -TrapType REDStateException::_trapType = 0x005; -FaultPriority REDStateException::_priority = 1; -FaultStat REDStateException::_count; - -FaultName InstructionAccessException::_name = "inst_access"; -TrapType InstructionAccessException::_trapType = 0x008; -FaultPriority InstructionAccessException::_priority = 5; -FaultStat InstructionAccessException::_count; - -FaultName InstructionAccessMMUMiss::_name = "inst_mmu"; -TrapType InstructionAccessMMUMiss::_trapType = 0x009; -FaultPriority InstructionAccessMMUMiss::_priority = 2; -FaultStat InstructionAccessMMUMiss::_count; - -FaultName InstructionAccessError::_name = "inst_error"; -TrapType InstructionAccessError::_trapType = 0x00A; -FaultPriority InstructionAccessError::_priority = 3; -FaultStat InstructionAccessError::_count; - -FaultName IllegalInstruction::_name = "illegal_inst"; -TrapType IllegalInstruction::_trapType = 0x010; -FaultPriority IllegalInstruction::_priority = 7; -FaultStat IllegalInstruction::_count; - -FaultName PrivilegedOpcode::_name = "priv_opcode"; -TrapType PrivilegedOpcode::_trapType = 0x011; -FaultPriority PrivilegedOpcode::_priority = 6; -FaultStat PrivilegedOpcode::_count; - -FaultName UnimplementedLDD::_name = "unimp_ldd"; -TrapType UnimplementedLDD::_trapType = 0x012; -FaultPriority UnimplementedLDD::_priority = 6; -FaultStat UnimplementedLDD::_count; - -FaultName UnimplementedSTD::_name = "unimp_std"; -TrapType UnimplementedSTD::_trapType = 0x013; -FaultPriority UnimplementedSTD::_priority = 6; -FaultStat UnimplementedSTD::_count; - -FaultName FpDisabled::_name = "fp_disabled"; -TrapType FpDisabled::_trapType = 0x020; -FaultPriority FpDisabled::_priority = 8; -FaultStat FpDisabled::_count; - -FaultName FpExceptionIEEE754::_name = "fp_754"; -TrapType FpExceptionIEEE754::_trapType = 0x021; -FaultPriority FpExceptionIEEE754::_priority = 11; -FaultStat FpExceptionIEEE754::_count; - -FaultName FpExceptionOther::_name = "fp_other"; -TrapType FpExceptionOther::_trapType = 0x022; -FaultPriority FpExceptionOther::_priority = 11; -FaultStat FpExceptionOther::_count; - -FaultName TagOverflow::_name = "tag_overflow"; -TrapType TagOverflow::_trapType = 0x023; -FaultPriority TagOverflow::_priority = 14; -FaultStat TagOverflow::_count; - -FaultName DivisionByZero::_name = "div_by_zero"; -TrapType DivisionByZero::_trapType = 0x028; -FaultPriority DivisionByZero::_priority = 15; -FaultStat DivisionByZero::_count; - -FaultName DataAccessException::_name = "data_access"; -TrapType DataAccessException::_trapType = 0x030; -FaultPriority DataAccessException::_priority = 12; -FaultStat DataAccessException::_count; - -FaultName DataAccessMMUMiss::_name = "data_mmu"; -TrapType DataAccessMMUMiss::_trapType = 0x031; -FaultPriority DataAccessMMUMiss::_priority = 12; -FaultStat DataAccessMMUMiss::_count; - -FaultName DataAccessError::_name = "data_error"; -TrapType DataAccessError::_trapType = 0x032; -FaultPriority DataAccessError::_priority = 12; -FaultStat DataAccessError::_count; - -FaultName DataAccessProtection::_name = "data_protection"; -TrapType DataAccessProtection::_trapType = 0x033; -FaultPriority DataAccessProtection::_priority = 12; -FaultStat DataAccessProtection::_count; - -FaultName LDDFMemAddressNotAligned::_name = "unalign_lddf"; -TrapType LDDFMemAddressNotAligned::_trapType = 0x035; -FaultPriority LDDFMemAddressNotAligned::_priority = 10; -FaultStat LDDFMemAddressNotAligned::_count; - -FaultName STDFMemAddressNotAligned::_name = "unalign_stdf"; -TrapType STDFMemAddressNotAligned::_trapType = 0x036; -FaultPriority STDFMemAddressNotAligned::_priority = 10; -FaultStat STDFMemAddressNotAligned::_count; - -FaultName PrivilegedAction::_name = "priv_action"; -TrapType PrivilegedAction::_trapType = 0x037; -FaultPriority PrivilegedAction::_priority = 11; -FaultStat PrivilegedAction::_count; - -FaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf"; -TrapType LDQFMemAddressNotAligned::_trapType = 0x038; -FaultPriority LDQFMemAddressNotAligned::_priority = 10; -FaultStat LDQFMemAddressNotAligned::_count; - -FaultName STQFMemAddressNotAligned::_name = "unalign_stqf"; -TrapType STQFMemAddressNotAligned::_trapType = 0x039; -FaultPriority STQFMemAddressNotAligned::_priority = 10; -FaultStat STQFMemAddressNotAligned::_count; - -FaultName AsyncDataError::_name = "async_data"; -TrapType AsyncDataError::_trapType = 0x040; -FaultPriority AsyncDataError::_priority = 2; -FaultStat AsyncDataError::_count; - -FaultName CleanWindow::_name = "clean_win"; -TrapType CleanWindow::_trapType = 0x024; -FaultPriority CleanWindow::_priority = 10; -FaultStat CleanWindow::_count; +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"intprocerr", 0x029, 4}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"unalign", 0x034, 10}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"pow_reset", 0x001, 0}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"watch_dog_reset", 0x002, 1}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"extern_reset", 0x003, 1}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"software_reset", 0x004, 1}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"red_counte", 0x005, 1}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"inst_access", 0x008, 5}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"inst_mmu", 0x009, 2}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"inst_error", 0x00A, 3}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"illegal_inst", 0x010, 7}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"priv_opcode", 0x011, 6}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"unimp_ldd", 0x012, 6}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"unimp_std", 0x013, 6}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"fp_disabled", 0x020, 8}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"fp_754", 0x021, 11}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"fp_other", 0x022, 11}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"tag_overflow", 0x023, 14}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"div_by_zero", 0x028, 15}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"data_access", 0x030, 12}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"data_mmu", 0x031, 12}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"data_error", 0x032, 12}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"data_protection", 0x033, 12}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"unalign_lddf", 0x035, 10}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"unalign_stdf", 0x036, 10}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"priv_action", 0x037, 11}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"unalign_ldqf", 0x038, 10}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"unalign_stqf", 0x039, 10}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"async_data", 0x040, 2}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"clean_win", 0x024, 10}; //The enumerated faults -FaultName InterruptLevelN::_name = "interrupt_n"; -TrapType InterruptLevelN::_baseTrapType = 0x041; -FaultStat InterruptLevelN::_count; +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"interrupt_n", 0x041, 0}; -FaultName SpillNNormal::_name = "spill_n_normal"; -TrapType SpillNNormal::_baseTrapType = 0x080; -FaultPriority SpillNNormal::_priority = 9; -FaultStat SpillNNormal::_count; +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"spill_n_normal", 0x080, 9}; -FaultName SpillNOther::_name = "spill_n_other"; -TrapType SpillNOther::_baseTrapType = 0x0A0; -FaultPriority SpillNOther::_priority = 9; -FaultStat SpillNOther::_count; +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"spill_n_other", 0x0A0, 9}; -FaultName FillNNormal::_name = "fill_n_normal"; -TrapType FillNNormal::_baseTrapType = 0x0C0; -FaultPriority FillNNormal::_priority = 9; -FaultStat FillNNormal::_count; +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"fill_n_normal", 0x0C0, 9}; -FaultName FillNOther::_name = "fill_n_other"; -TrapType FillNOther::_baseTrapType = 0x0E0; -FaultPriority FillNOther::_priority = 9; -FaultStat FillNOther::_count; +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"fill_n_other", 0x0E0, 9}; -FaultName TrapInstruction::_name = "trap_inst_n"; -TrapType TrapInstruction::_baseTrapType = 0x100; -FaultPriority TrapInstruction::_priority = 16; -FaultStat TrapInstruction::_count; +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"trap_inst_n", 0x100, 16}; #if !FULL_SYSTEM -FaultName PageTableFault::_name = "page_table_fault"; -TrapType PageTableFault::_trapType = 0x0000; -FaultPriority PageTableFault::_priority = 0; -FaultStat PageTableFault::_count; +template<> SparcFaultBase::FaultVals + SparcFault::vals = {"page_table_fault", 0x0000, 0}; #endif /** @@ -353,7 +280,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt) #if FULL_SYSTEM -void SparcFault::invoke(ThreadContext * tc) +void SparcFaultBase::invoke(ThreadContext * tc) { FaultBase::invoke(tc); countStat()++; diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 394a06294..22f83c1e5 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -42,63 +42,58 @@ namespace SparcISA typedef uint32_t TrapType; typedef uint32_t FaultPriority; -class SparcFault : public FaultBase +class SparcFaultBase : public FaultBase { public: + struct FaultVals + { + const FaultName name; + const TrapType trapType; + const FaultPriority priority; + FaultStat count; + }; #if FULL_SYSTEM void invoke(ThreadContext * tc); #endif + virtual FaultName name() = 0; virtual TrapType trapType() = 0; virtual FaultPriority priority() = 0; virtual FaultStat & countStat() = 0; }; -class InternalProcessorError : public SparcFault +template +class SparcFault : public SparcFaultBase +{ + protected: + static FaultVals vals; + public: + FaultName name() {return vals.name;} + TrapType trapType() {return vals.trapType;} + FaultPriority priority() {return vals.priority;} + FaultStat & countStat() {return vals.count;} +}; + +class InternalProcessorError : + public SparcFault { - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} bool isMachineCheckFault() {return true;} }; -class MemAddressNotAligned : public SparcFault +class MemAddressNotAligned : + public SparcFault { - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} bool isAlignmentFault() {return true;} }; #if !FULL_SYSTEM -class PageTableFault : public SparcFault +class PageTableFault : public SparcFault { private: Addr vaddr; - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; public: - PageTableFault(Addr va) - : vaddr(va) {} - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} + PageTableFault(Addr va) : vaddr(va) {} void invoke(ThreadContext * tc); }; @@ -118,499 +113,117 @@ static inline Fault genAlignmentFault() return new MemAddressNotAligned; } -class PowerOnReset : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class PowerOnReset : public SparcFault {}; -class WatchDogReset : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class WatchDogReset : public SparcFault {}; -class ExternallyInitiatedReset : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class ExternallyInitiatedReset : public SparcFault {}; -class SoftwareInitiatedReset : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class SoftwareInitiatedReset : public SparcFault {}; -class REDStateException : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class REDStateException : public SparcFault {}; -class InstructionAccessException : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class InstructionAccessException : public SparcFault {}; -class InstructionAccessMMUMiss : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class InstructionAccessMMUMiss : public SparcFault {}; -class InstructionAccessError : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class InstructionAccessError : public SparcFault {}; -class IllegalInstruction : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class IllegalInstruction : public SparcFault {}; -class PrivilegedOpcode : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class PrivilegedOpcode : public SparcFault {}; -class UnimplementedLDD : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class UnimplementedLDD : public SparcFault {}; -class UnimplementedSTD : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class UnimplementedSTD : public SparcFault {}; -class FpDisabled : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class FpDisabled : public SparcFault {}; -class FpExceptionIEEE754 : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class FpExceptionIEEE754 : public SparcFault {}; -class FpExceptionOther : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class FpExceptionOther : public SparcFault {}; -class TagOverflow : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class TagOverflow : public SparcFault {}; -class DivisionByZero : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class DivisionByZero : public SparcFault {}; -class DataAccessException : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class DataAccessException : public SparcFault {}; -class DataAccessMMUMiss : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class DataAccessMMUMiss : public SparcFault {}; -class DataAccessError : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class DataAccessError : public SparcFault {}; -class DataAccessProtection : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class DataAccessProtection : public SparcFault {}; -class LDDFMemAddressNotAligned : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class LDDFMemAddressNotAligned : public SparcFault {}; -class STDFMemAddressNotAligned : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class STDFMemAddressNotAligned : public SparcFault {}; -class PrivilegedAction : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class PrivilegedAction : public SparcFault {}; -class LDQFMemAddressNotAligned : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class LDQFMemAddressNotAligned : public SparcFault {}; -class STQFMemAddressNotAligned : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class STQFMemAddressNotAligned : public SparcFault {}; -class AsyncDataError : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class AsyncDataError : public SparcFault {}; -class CleanWindow : public SparcFault -{ - private: - static FaultName _name; - static TrapType _trapType; - static FaultPriority _priority; - static FaultStat _count; - public: - FaultName name() {return _name;} - TrapType trapType() {return _trapType;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} -}; +class CleanWindow : public SparcFault {}; -class EnumeratedFault : public SparcFault +template +class EnumeratedFault : public SparcFault { protected: uint32_t _n; - virtual TrapType baseTrapType() = 0; public: - EnumeratedFault(uint32_t n) : SparcFault() {_n = n;} - TrapType trapType() {return baseTrapType() + _n;} + EnumeratedFault(uint32_t n) : SparcFault(), _n(n) {} + TrapType trapType() {return SparcFault::trapType() + _n;} }; -class InterruptLevelN : public EnumeratedFault +class InterruptLevelN : public EnumeratedFault { - private: - static FaultName _name; - static TrapType _baseTrapType; - static FaultStat _count; - TrapType baseTrapType() {return _baseTrapType;} public: - InterruptLevelN(uint32_t n) : EnumeratedFault(n) {;} - FaultName name() {return _name;} + InterruptLevelN(uint32_t n) : + EnumeratedFault(n) {;} FaultPriority priority() {return 32 - _n;} - FaultStat & countStat() {return _count;} }; -class SpillNNormal : public EnumeratedFault +class SpillNNormal : public EnumeratedFault { - private: - static FaultName _name; - static TrapType _baseTrapType; - static FaultPriority _priority; - static FaultStat _count; - TrapType baseTrapType() {return _baseTrapType;} public: - SpillNNormal(uint32_t n) : EnumeratedFault(n) {;} - FaultName name() {return _name;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} + SpillNNormal(uint32_t n) : + EnumeratedFault(n) {;} void invoke(ThreadContext * tc); }; -class SpillNOther : public EnumeratedFault +class SpillNOther : public EnumeratedFault { - private: - static FaultName _name; - static TrapType _baseTrapType; - static FaultPriority _priority; - static FaultStat _count; - TrapType baseTrapType() {return _baseTrapType;} public: - SpillNOther(uint32_t n) : EnumeratedFault(n) {;} - FaultName name() {return _name;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} + SpillNOther(uint32_t n) : + EnumeratedFault(n) {;} }; -class FillNNormal : public EnumeratedFault +class FillNNormal : public EnumeratedFault { - private: - static FaultName _name; - static TrapType _baseTrapType; - static FaultPriority _priority; - static FaultStat _count; - TrapType baseTrapType() {return _baseTrapType;} public: - FillNNormal(uint32_t n) : EnumeratedFault(n) {;} - FaultName name() {return _name;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} + FillNNormal(uint32_t n) : + EnumeratedFault(n) {;} void invoke(ThreadContext * tc); }; -class FillNOther : public EnumeratedFault +class FillNOther : public EnumeratedFault { - private: - static FaultName _name; - static TrapType _baseTrapType; - static FaultPriority _priority; - static FaultStat _count; - TrapType baseTrapType() {return _baseTrapType;} public: - FillNOther(uint32_t n) : EnumeratedFault(n) {;} - FaultName name() {return _name;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} + FillNOther(uint32_t n) : + EnumeratedFault(n) {;} }; -class TrapInstruction : public EnumeratedFault +class TrapInstruction : public EnumeratedFault { private: - static FaultName _name; - static TrapType _baseTrapType; - static FaultPriority _priority; - static FaultStat _count; uint64_t syscall_num; - TrapType baseTrapType() {return _baseTrapType;} public: TrapInstruction(uint32_t n, uint64_t syscall) : - EnumeratedFault(n), syscall_num(syscall) {;} - FaultName name() {return _name;} - FaultPriority priority() {return _priority;} - FaultStat & countStat() {return _count;} + EnumeratedFault(n), syscall_num(syscall) {;} #if !FULL_SYSTEM void invoke(ThreadContext * tc); #endif -- cgit v1.2.3 From 9375caa3f1ac8ff8fe5bcf3b7de1f51a20b6cd91 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 08:25:37 -0500 Subject: Fix for slightly mangled merge. --HG-- extra : convert_revision : 1dea04ca222dd423c3d462114bc1c65afa52825d --- src/arch/sparc/faults.hh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 677f8e77e..9cc7739d9 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -228,9 +228,10 @@ class FillNOther : public EnumeratedFault class TrapInstruction : public EnumeratedFault { + public: - TrapInstruction(uint32_t n, uint64_t syscall) : - EnumeratedFault(n), syscall_num(syscall) {;} + TrapInstruction(uint32_t n) : + EnumeratedFault(n) {;} }; -- cgit v1.2.3 From 770b575c30e734b3ed9528558a72c476a9e4bf41 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 10:27:38 -0500 Subject: Sorted faults by the trap type constant, expanded their names, added in new faults for ua2005, and commented out ones which are apparently dropped. --HG-- extra : convert_revision : 32bd0c3a75d7c036ad4a3cb0bc1c32e0b6cb3d87 --- src/arch/sparc/faults.cc | 180 +++++++++++++++++++++++++++++++++++++---------- src/arch/sparc/faults.hh | 161 ++++++++++++++++++++++++++---------------- 2 files changed, 244 insertions(+), 97 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 6a905a76c..ebd9926b2 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -50,118 +50,222 @@ namespace SparcISA { template<> SparcFaultBase::FaultVals - SparcFault::vals = {"intprocerr", 0x029, 4}; + SparcFault::vals = + {"power_on_reset", 0x001, 0, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"unalign", 0x034, 10}; + SparcFault::vals = + {"watch_dog_reset", 0x002, 120, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"pow_reset", 0x001, 0}; + SparcFault::vals = + {"externally_initiated_reset", 0x003, 110, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"watch_dog_reset", 0x002, 1}; + SparcFault::vals = + {"software_initiated_reset", 0x004, 130, {SH, SH, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"extern_reset", 0x003, 1}; + SparcFault::vals = + {"RED_state_exception", 0x005, 1, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"software_reset", 0x004, 1}; + SparcFault::vals = + {"store_error", 0x007, 201, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"red_counte", 0x005, 1}; + SparcFault::vals = + {"instruction_access_exception", 0x008, 300, {H, H, H}}; + +//XXX This trap is apparently dropped from ua2005 +/*template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"inst_mmu", 0x009, 2, {H, H, H}};*/ + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"instruction_access_error", 0x00A, 400, {H, H, H}}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"illegal_instruction", 0x010, 620, {H, H, H}}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"privileged_opcode", 0x011, 700, {P, SH, SH}}; + +//XXX This trap is apparently dropped from ua2005 +/*template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"unimp_ldd", 0x012, 6, {H, H, H}};*/ + +//XXX This trap is apparently dropped from ua2005 +/*template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"unimp_std", 0x013, 6, {H, H, H}};*/ + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"fp_disabled", 0x020, 800, {P, P, H}}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"inst_access", 0x008, 5}; + SparcFault::vals = + {"fp_exception_other", 0x022, 1110, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"inst_mmu", 0x009, 2}; + SparcFault::vals = + {"tag_overflow", 0x023, 1400, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"inst_error", 0x00A, 3}; + SparcFault::vals = + {"clean_window", 0x024, 1010, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"illegal_inst", 0x010, 7}; + SparcFault::vals = + {"division_by_zero", 0x028, 1500, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"priv_opcode", 0x011, 6}; + SparcFault::vals = + {"internal_processor_error", 0x029, 4, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"unimp_ldd", 0x012, 6}; + SparcFault::vals = + {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"unimp_std", 0x013, 6}; + SparcFault::vals = + {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"fp_disabled", 0x020, 8}; + SparcFault::vals = + {"data_access_exception", 0x030, 1201, {H, H, H}}; + +//XXX This trap is apparently dropped from ua2005 +/*template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"data_mmu", 0x031, 12, {H, H, H}};*/ + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"data_access_error", 0x032, 1210, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"fp_754", 0x021, 11}; + SparcFault::vals = + {"data_access_protection", 0x033, 1207, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"fp_other", 0x022, 11}; + SparcFault::vals = + {"mem_address_not_aligned", 0x034, 1020, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"tag_overflow", 0x023, 14}; + SparcFault::vals = + {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"div_by_zero", 0x028, 15}; + SparcFault::vals = + {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"data_access", 0x030, 12}; + SparcFault::vals = + {"privileged_action", 0x037, 1110, {H, H, SH}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"data_mmu", 0x031, 12}; + SparcFault::vals = + {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"data_error", 0x032, 12}; + SparcFault::vals = + {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"data_protection", 0x033, 12}; + SparcFault::vals = + {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"unalign_lddf", 0x035, 10}; + SparcFault::vals = + {"data_real_translation_miss", 0x03F, 1203, {H, H, H}}; + +//XXX This trap is apparently dropped from ua2005 +/*template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"async_data", 0x040, 2, {H, H, H}};*/ template<> SparcFaultBase::FaultVals - SparcFault::vals = {"unalign_stdf", 0x036, 10}; + SparcFault::vals = + {"interrupt_level_n", 0x041, 0, {P, P, SH}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"priv_action", 0x037, 11}; + SparcFault::vals = + {"hstick_match", 0x05E, 1601, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"unalign_ldqf", 0x038, 10}; + SparcFault::vals = + {"trap_level_zero", 0x05F, 202, {H, H, SH}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"unalign_stqf", 0x039, 10}; + SparcFault::vals = + {"PA_watchpoint", 0x061, 1209, {H, H, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"async_data", 0x040, 2}; + SparcFault::vals = + {"VA_watchpoint", 0x062, 1120, {P, P, SH}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"clean_win", 0x024, 10}; + SparcFault::vals = + {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}}; -//The enumerated faults +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"fast_data_access_protection", 0x06C, 1207, {H, H, H}}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"instruction_break", 0x076, 610, {H, H, H}}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"cpu_mondo", 0x07C, 1608, {P, P, SH}}; + +template<> SparcFaultBase::FaultVals + SparcFault::vals = + {"dev_mondo", 0x07D, 1611, {P, P, SH}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"interrupt_n", 0x041, 0}; + SparcFault::vals = + {"resume_error", 0x07E, 3330, {P, P, SH}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"spill_n_normal", 0x080, 9}; + SparcFault::vals = + {"spill_n_normal", 0x080, 900, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"spill_n_other", 0x0A0, 9}; + SparcFault::vals = + {"spill_n_other", 0x0A0, 900, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"fill_n_normal", 0x0C0, 9}; + SparcFault::vals = + {"fill_n_normal", 0x0C0, 900, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"fill_n_other", 0x0E0, 9}; + SparcFault::vals = + {"fill_n_other", 0x0E0, 900, {P, P, H}}; template<> SparcFaultBase::FaultVals - SparcFault::vals = {"trap_inst_n", 0x100, 16}; + SparcFault::vals = + {"trap_instruction", 0x100, 1602, {P, P, H}}; #if !FULL_SYSTEM template<> SparcFaultBase::FaultVals - SparcFault::vals = {"page_table_fault", 0x0000, 0}; + SparcFault::vals = + {"page_table_fault", 0x0000, 0, {SH, SH, SH}}; #endif /** diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 9cc7739d9..e632502aa 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -45,11 +45,21 @@ typedef uint32_t FaultPriority; class SparcFaultBase : public FaultBase { public: + enum PrivilegeLevel + { + U, User = U, + P, Privileged = P, + H, Hyperprivileged = H, + NumLevels, + SH = -1, + ShouldntHappen = SH + }; struct FaultVals { const FaultName name; const TrapType trapType; const FaultPriority priority; + const PrivilegeLevel nextPrivilegeLevel[NumLevels]; FaultStat count; }; #if FULL_SYSTEM @@ -59,6 +69,7 @@ class SparcFaultBase : public FaultBase virtual TrapType trapType() = 0; virtual FaultPriority priority() = 0; virtual FaultStat & countStat() = 0; + virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0; }; template @@ -71,48 +82,12 @@ class SparcFault : public SparcFaultBase TrapType trapType() {return vals.trapType;} FaultPriority priority() {return vals.priority;} FaultStat & countStat() {return vals.count;} + PrivilegeLevel getNextLevel(PrivilegeLevel current) + { + return vals.nextPrivilegeLevel[current]; + } }; -class InternalProcessorError : - public SparcFault -{ - public: - bool isMachineCheckFault() {return true;} -}; - -class MemAddressNotAligned : - public SparcFault -{ - public: - bool isAlignmentFault() {return true;} -}; - -#if !FULL_SYSTEM -class PageTableFault : public SparcFault -{ - private: - Addr vaddr; - public: - PageTableFault(Addr va) : vaddr(va) {} - void invoke(ThreadContext * tc); -}; - -static inline Fault genPageTableFault(Addr va) -{ - return new PageTableFault(va); -} -#endif - -static inline Fault genMachineCheckFault() -{ - return new InternalProcessorError; -} - -static inline Fault genAlignmentFault() -{ - return new MemAddressNotAligned; -} - class PowerOnReset : public SparcFault { void invoke(ThreadContext * tc); @@ -126,9 +101,11 @@ class SoftwareInitiatedReset : public SparcFault {}; class REDStateException : public SparcFault {}; +class StoreError : public SparcFault {}; + class InstructionAccessException : public SparcFault {}; -class InstructionAccessMMUMiss : public SparcFault {}; +//class InstructionAccessMMUMiss : public SparcFault {}; class InstructionAccessError : public SparcFault {}; @@ -136,9 +113,9 @@ class IllegalInstruction : public SparcFault {}; class PrivilegedOpcode : public SparcFault {}; -class UnimplementedLDD : public SparcFault {}; +//class UnimplementedLDD : public SparcFault {}; -class UnimplementedSTD : public SparcFault {}; +//class UnimplementedSTD : public SparcFault {}; class FpDisabled : public SparcFault {}; @@ -148,16 +125,36 @@ class FpExceptionOther : public SparcFault {}; class TagOverflow : public SparcFault {}; +class CleanWindow : public SparcFault {}; + class DivisionByZero : public SparcFault {}; +class InternalProcessorError : + public SparcFault +{ + public: + bool isMachineCheckFault() {return true;} +}; + +class InstructionInvalidTSBEntry : public SparcFault {}; + +class DataInvalidTSBEntry : public SparcFault {}; + class DataAccessException : public SparcFault {}; -class DataAccessMMUMiss : public SparcFault {}; +//class DataAccessMMUMiss : public SparcFault {}; class DataAccessError : public SparcFault {}; class DataAccessProtection : public SparcFault {}; +class MemAddressNotAligned : + public SparcFault +{ + public: + bool isAlignmentFault() {return true;} +}; + class LDDFMemAddressNotAligned : public SparcFault {}; class STDFMemAddressNotAligned : public SparcFault {}; @@ -168,9 +165,12 @@ class LDQFMemAddressNotAligned : public SparcFault {}; class STQFMemAddressNotAligned : public SparcFault {}; -class AsyncDataError : public SparcFault {}; +class InstructionRealTranslationMiss : + public SparcFault {}; -class CleanWindow : public SparcFault {}; +class DataRealTranslationMiss : public SparcFault {}; + +//class AsyncDataError : public SparcFault {}; template class EnumeratedFault : public SparcFault @@ -185,16 +185,37 @@ class EnumeratedFault : public SparcFault class InterruptLevelN : public EnumeratedFault { public: - InterruptLevelN(uint32_t n) : - EnumeratedFault(n) {;} - FaultPriority priority() {return 32 - _n;} + InterruptLevelN(uint32_t n) : EnumeratedFault(n) {;} + FaultPriority priority() {return 3200 - _n*100;} }; +class HstickMatch : public SparcFault {}; + +class TrapLevelZero : public SparcFault {}; + +class PAWatchpoint : public SparcFault {}; + +class VAWatchpoint : public SparcFault {}; + +class FastInstructionAccessMMUMiss : + public SparcFault {}; + +class FastDataAccessMMUMiss : public SparcFault {}; + +class FastDataAccessProtection : public SparcFault {}; + +class InstructionBreakpoint : public SparcFault {}; + +class CpuMondo : public SparcFault {}; + +class DevMondo : public SparcFault {}; + +class ResumeableError : public SparcFault {}; + class SpillNNormal : public EnumeratedFault { public: - SpillNNormal(uint32_t n) : - EnumeratedFault(n) {;} + SpillNNormal(uint32_t n) : EnumeratedFault(n) {;} //These need to be handled specially to enable spill traps in SE #if !FULL_SYSTEM void invoke(ThreadContext * tc); @@ -204,15 +225,13 @@ class SpillNNormal : public EnumeratedFault class SpillNOther : public EnumeratedFault { public: - SpillNOther(uint32_t n) : - EnumeratedFault(n) {;} + SpillNOther(uint32_t n) : EnumeratedFault(n) {;} }; class FillNNormal : public EnumeratedFault { public: - FillNNormal(uint32_t n) : - EnumeratedFault(n) {;} + FillNNormal(uint32_t n) : EnumeratedFault(n) {;} //These need to be handled specially to enable fill traps in SE #if !FULL_SYSTEM void invoke(ThreadContext * tc); @@ -222,18 +241,42 @@ class FillNNormal : public EnumeratedFault class FillNOther : public EnumeratedFault { public: - FillNOther(uint32_t n) : - EnumeratedFault(n) {;} + FillNOther(uint32_t n) : EnumeratedFault(n) {;} }; class TrapInstruction : public EnumeratedFault { public: - TrapInstruction(uint32_t n) : - EnumeratedFault(n) {;} + TrapInstruction(uint32_t n) : EnumeratedFault(n) {;} +}; + +#if !FULL_SYSTEM +class PageTableFault : public SparcFault +{ + private: + Addr vaddr; + public: + PageTableFault(Addr va) : vaddr(va) {} + void invoke(ThreadContext * tc); }; +static inline Fault genPageTableFault(Addr va) +{ + return new PageTableFault(va); +} +#endif + +static inline Fault genMachineCheckFault() +{ + return new InternalProcessorError; +} + +static inline Fault genAlignmentFault() +{ + return new MemAddressNotAligned; +} + } // SparcISA namespace -- cgit v1.2.3 From 67b9a2ebd850b6b0a01324b46ac3d6f87b3a8cb5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 13:55:48 -0500 Subject: Move the check to see if you're in user mode into the isa directory. --HG-- extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6 --- src/arch/alpha/utility.hh | 6 ++++++ src/arch/sparc/utility.hh | 8 ++++++++ 2 files changed, 14 insertions(+) (limited to 'src/arch') diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index cb86c7e9e..100736555 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -42,6 +42,12 @@ namespace AlphaISA { + static inline bool + inUserMode(ThreadContext *tc) + { + return (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + } + static inline ExtMachInst makeExtMI(MachInst inst, Addr pc) { #if FULL_SYSTEM diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index e2b0b2307..e51677cdf 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -39,6 +39,14 @@ namespace SparcISA { + + static inline bool + inUserMode(ThreadContext *tc) + { + return !(tc->readMiscReg(MISCREG_PSTATE & (1 << 2)) || + tc->readMiscReg(MISCREG_HPSTATE & (1 << 2))); + } + inline ExtMachInst makeExtMI(MachInst inst, ThreadContext * xc) { ExtMachInst emi = (unsigned MachInst) inst; -- cgit v1.2.3 From 63bbc8929d778c15f5c7479819226c19a42dc2b9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 13:58:00 -0500 Subject: First cut at full blown SPARC faults. There are a few details that are missing. --HG-- extra : convert_revision : 8023db1479cb9bf99fc9edfeb521c4e5b581f895 --- src/arch/sparc/faults.cc | 240 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 211 insertions(+), 29 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index ebd9926b2..e895c02db 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -33,6 +33,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/types.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "config/full_system.hh" @@ -268,26 +269,133 @@ template<> SparcFaultBase::FaultVals {"page_table_fault", 0x0000, 0, {SH, SH, SH}}; #endif +/** + * This causes the thread context to enter RED state. This causes the side + * effects which go with entering RED state because of a trap. + */ + +void enterREDState(ThreadContext *tc) +{ + //@todo Disable the mmu? + //@todo Disable watchpoints? + MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); + //HPSTATE.red = 1 + HPSTATE |= (1 << 5); + //HPSTATE.hpriv = 1 + HPSTATE |= (1 << 2); + tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); +} + +/** + * This sets everything up for a RED state trap except for actually jumping to + * the handler. + */ + +void doREDFault(ThreadContext *tc, TrapType tt) +{ + MiscReg TL = tc->readMiscReg(MISCREG_TL); + MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE); + MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); + MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); + MiscReg CCR = tc->readMiscReg(MISCREG_CCR); + MiscReg ASI = tc->readMiscReg(MISCREG_ASI); + MiscReg CWP = tc->readMiscReg(MISCREG_CWP); + MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); + MiscReg GL = tc->readMiscReg(MISCREG_GL); + MiscReg PC = tc->readPC(); + MiscReg NPC = tc->readNextPC(); + + TL++; + + //set TSTATE.gl to gl + replaceBits(TSTATE, 42, 40, GL); + //set TSTATE.ccr to ccr + replaceBits(TSTATE, 39, 32, CCR); + //set TSTATE.asi to asi + replaceBits(TSTATE, 31, 24, ASI); + //set TSTATE.pstate to pstate + replaceBits(TSTATE, 20, 8, PSTATE); + //set TSTATE.cwp to cwp + replaceBits(TSTATE, 4, 0, CWP); + + //Write back TSTATE + tc->setMiscReg(MISCREG_TSTATE, TSTATE); + + //set TPC to PC + tc->setMiscReg(MISCREG_TPC, PC); + //set TNPC to NPC + tc->setMiscReg(MISCREG_TNPC, NPC); + + //set HTSTATE.hpstate to hpstate + tc->setMiscReg(MISCREG_HTSTATE, HPSTATE); + + //TT = trap type; + tc->setMiscReg(MISCREG_TT, tt); + + //Update GL + tc->setMiscRegWithEffect(MISCREG_GL, min(GL+1, MaxGL)); + + //set PSTATE.mm to 00 + //set PSTATE.pef to 1 + PSTATE |= (1 << 4); + //set PSTATE.am to 0 + PSTATE &= ~(1 << 3); + //set PSTATE.priv to 0 + PSTATE &= ~(1 << 2); + //set PSTATE.ie to 0 + PSTATE &= ~(1 << 1); + //set PSTATE.cle to 0 + PSTATE &= ~(1 << 9); + //PSTATE.tle is unchanged + //XXX Where is the tct bit? + //set PSTATE.tct to 0 + tc->setMiscReg(MISCREG_PSTATE, PSTATE); + + //set HPSTATE.red to 1 + HPSTATE |= (1 << 5); + //set HPSTATE.hpriv to 1 + HPSTATE |= (1 << 2); + //set HPSTATE.ibe to 0 + HPSTATE &= ~(1 << 10); + //set HPSTATE.tlz to 0 + HPSTATE &= ~(1 << 0); + tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); + + bool changedCWP = true; + if(tt == 0x24) + CWP++; + else if(0x80 <= tt && tt <= 0xbf) + CWP += (CANSAVE + 2); + else if(0xc0 <= tt && tt <= 0xff) + CWP--; + else + changedCWP = false; + + if(changedCWP) + { + CWP = (CWP + NWindows) % NWindows; + tc->setMiscRegWithEffect(MISCREG_CWP, CWP); + } +} + /** * This sets everything up for a normal trap except for actually jumping to - * the handler. It will need to be expanded to include the state machine in - * the manual. Right now it assumes that traps will always be to the - * privileged level. + * the handler. */ -void doNormalFault(ThreadContext *tc, TrapType tt) +void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) { - uint64_t TL = tc->readMiscReg(MISCREG_TL); - uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE); - uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE); - uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); - uint64_t CCR = tc->readMiscReg(MISCREG_CCR); - uint64_t ASI = tc->readMiscReg(MISCREG_ASI); - uint64_t CWP = tc->readMiscReg(MISCREG_CWP); - uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); - uint64_t GL = tc->readMiscReg(MISCREG_GL); - uint64_t PC = tc->readPC(); - uint64_t NPC = tc->readNextPC(); + MiscReg TL = tc->readMiscReg(MISCREG_TL); + MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE); + MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); + MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); + MiscReg CCR = tc->readMiscReg(MISCREG_CCR); + MiscReg ASI = tc->readMiscReg(MISCREG_ASI); + MiscReg CWP = tc->readMiscReg(MISCREG_CWP); + MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); + MiscReg GL = tc->readMiscReg(MISCREG_GL); + MiscReg PC = tc->readPC(); + MiscReg NPC = tc->readNextPC(); //Increment the trap level TL++; @@ -321,10 +429,10 @@ void doNormalFault(ThreadContext *tc, TrapType tt) tc->setMiscReg(MISCREG_TT, tt); //Update the global register level - if(1/*We're delivering the trap in priveleged mode*/) - tc->setMiscReg(MISCREG_GL, min(GL+1, MaxGL)); + if(!gotoHpriv) + tc->setMiscRegWithEffect(MISCREG_GL, min(GL+1, MaxPGL)); else - tc->setMiscReg(MISCREG_GL, min(GL+1, MaxPGL)); + tc->setMiscRegWithEffect(MISCREG_GL, min(GL+1, MaxGL)); //PSTATE.mm is unchanged //PSTATE.pef = whether or not an fpu is present @@ -333,7 +441,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt) PSTATE |= (1 << 4); //PSTATE.am = 0 PSTATE &= ~(1 << 3); - if(1/*We're delivering the trap in priveleged mode*/) + if(!gotoHpriv) { //PSTATE.priv = 1 PSTATE |= (1 << 2); @@ -354,7 +462,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt) //XXX Where exactly is this field? tc->setMiscReg(MISCREG_PSTATE, PSTATE); - if(0/*We're delivering the trap in hyperprivileged mode*/) + if(gotoHpriv) { //HPSTATE.red = 0 HPSTATE &= ~(1 << 5); @@ -383,6 +491,29 @@ void doNormalFault(ThreadContext *tc, TrapType tt) } } +void getREDVector(Addr & PC, Addr & NPC) +{ + const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL; + PC = RSTVAddr | 0xA0; + NPC = PC + sizeof(MachInst); +} + +void getHyperVector(Addr & PC, Addr & NPC, MiscReg TT) +{ + Addr HTBA ; + PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14)); + NPC = PC + sizeof(MachInst); +} + +void getPrivVector(Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL) +{ + Addr TBA ; + PC = (TBA & ~mask(15)) | + (TL > 1 ? (1 << 14) : 0) | + ((TT << 5) & mask(14)); + NPC = PC + sizeof(MachInst); +} + #if FULL_SYSTEM void SparcFaultBase::invoke(ThreadContext * tc) @@ -390,11 +521,64 @@ void SparcFaultBase::invoke(ThreadContext * tc) FaultBase::invoke(tc); countStat()++; - //Use the SPARC trap state machine + //We can refer to this to see what the trap level -was-, but something + //in the middle could change it in the regfile out from under us. + MiscReg TL = tc->readMiscReg(MISCREG_TL); + MiscReg TT = tc->readMiscReg(MISCREG_TT); + MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); + MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); + + Addr PC, NPC; + + PrivilegeLevel current; + if(!(PSTATE & (1 << 2))) + current = User; + else if(!(HPSTATE & (1 << 2))) + current = Privileged; + else + current = Hyperprivileged; + + PrivilegeLevel level = getNextLevel(current); + + if(HPSTATE & (1 << 5) || TL == MaxTL - 1) + { + getREDVector(PC, NPC); + enterREDState(tc); + doREDFault(tc, TT); + } + else if(TL == MaxTL) + { + //Do error_state somehow? + //Probably inject a WDR fault using the interrupt mechanism. + //What should the PC and NPC be set to? + } + else if(TL > MaxPTL && level == Privileged) + { + //guest_watchdog fault + doNormalFault(tc, trapType(), true); + getHyperVector(PC, NPC, 2); + } + else if(level == Hyperprivileged) + { + doNormalFault(tc, trapType(), true); + getHyperVector(PC, NPC, trapType()); + } + else + { + doNormalFault(tc, trapType(), false); + getPrivVector(PC, NPC, trapType(), TL+1); + } + + tc->setPC(PC); + tc->setNextPC(NPC); + tc->setNextNPC(NPC + sizeof(MachInst)); } void PowerOnReset::invoke(ThreadContext * tc) { + //First, enter RED state. + enterREDState(tc); + //For SPARC, when a system is first started, there is a power //on reset Trap which sets the processor into the following state. //Bits that aren't set aren't defined on startup. @@ -426,17 +610,15 @@ void PowerOnReset::invoke(ThreadContext * tc) */ } -#endif - -#if !FULL_SYSTEM +#else // !FULL_SYSTEM void SpillNNormal::invoke(ThreadContext *tc) { - doNormalFault(tc, trapType()); + doNormalFault(tc, trapType(), false); Process *p = tc->getProcessPtr(); - //This will only work in faults from a SparcLiveProcess + //XXX This will only work in faults from a SparcLiveProcess SparcLiveProcess *lp = dynamic_cast(p); assert(lp); @@ -449,15 +631,15 @@ void SpillNNormal::invoke(ThreadContext *tc) void FillNNormal::invoke(ThreadContext *tc) { - doNormalFault(tc, trapType()); + doNormalFault(tc, trapType(), false); Process * p = tc->getProcessPtr(); - //This will only work in faults from a SparcLiveProcess + //XXX This will only work in faults from a SparcLiveProcess SparcLiveProcess *lp = dynamic_cast(p); assert(lp); - //The adjust the PC and NPC + //Then adjust the PC and NPC Addr fillStart = lp->readFillStart(); tc->setPC(fillStart); tc->setNextPC(fillStart + sizeof(MachInst)); -- cgit v1.2.3 From 42c73c6a9215a46ec83e31e03aef9eddc281336f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 15:31:52 -0500 Subject: Make a function to say how big gdbregs is in bytes vs. regs. --HG-- extra : convert_revision : 10c50c2d45a8e510d71cccde520059363116da8a --- src/arch/alpha/remote_gdb.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index 829e41ca8..f23fc3205 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -141,7 +141,7 @@ using namespace TheISA; RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) : BaseRemoteGDB(_system, c, KGDB_NUMREGS) { - memset(gdbregs.regs, 0, gdbregs.size); + memset(gdbregs.regs, 0, gdbregs.bytes()); } /////////////////////////////////////////////////////////// @@ -201,7 +201,7 @@ RemoteGDB::acc(Addr va, size_t len) void RemoteGDB::getregs() { - memset(gdbregs.regs, 0, gdbregs.size); + memset(gdbregs.regs, 0, gdbregs.bytes()); gdbregs.regs[KGDB_REG_PC] = context->readPC(); -- cgit v1.2.3 From 5b90922ad59189f5967dc97a00bbfead062f4ba3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 16:15:20 -0500 Subject: Put the MIPS stacktrace into the MipsISA namespace to fit with Alpha and SPARC. --HG-- extra : convert_revision : 86f5585fe9ceb2ee30836d35384ebcddc1357c2a --- src/arch/mips/stacktrace.hh | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/arch') diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh index f9e092dbd..c854f63ca 100644 --- a/src/arch/mips/stacktrace.hh +++ b/src/arch/mips/stacktrace.hh @@ -37,6 +37,9 @@ class ThreadContext; class StackTrace; +namespace MipsISA +{ + class ProcessInfo { private: @@ -118,4 +121,6 @@ StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) return true; } +} + #endif // __ARCH_MIPS_STACKTRACE_HH__ -- cgit v1.2.3 From cb172d0332ecf4ff7f6329f1172d8e1cf78767e2 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 9 Nov 2006 18:22:46 -0500 Subject: Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work. SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together --HG-- extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af --- src/arch/sparc/system.cc | 42 +++++++++++++++++++++++++++++------------- src/arch/sparc/system.hh | 9 +++++++-- 2 files changed, 36 insertions(+), 15 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index 952ac2deb..4e907f002 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -42,39 +42,46 @@ using namespace BigEndianGuest; SparcSystem::SparcSystem(Params *p) - : System(p), sysTick(0) + : System(p), sysTick(0),funcRomPort(p->name + "-fport") { resetSymtab = new SymbolTable; hypervisorSymtab = new SymbolTable; openbootSymtab = new SymbolTable; + Port *rom_port; + rom_port = params()->rom->getPort("functional"); + funcRomPort.setPeer(rom_port); + rom_port->setPeer(&funcRomPort); /** * Load the boot code, and hypervisor into memory. */ // Read the reset binary - reset = createObjectFile(params()->reset_bin); + reset = createObjectFile(params()->reset_bin, true); if (reset == NULL) fatal("Could not load reset binary %s", params()->reset_bin); // Read the openboot binary - openboot = createObjectFile(params()->openboot_bin); + openboot = createObjectFile(params()->openboot_bin, true); if (openboot == NULL) fatal("Could not load openboot bianry %s", params()->openboot_bin); // Read the hypervisor binary - hypervisor = createObjectFile(params()->hypervisor_bin); + hypervisor = createObjectFile(params()->hypervisor_bin, true); if (hypervisor == NULL) fatal("Could not load hypervisor binary %s", params()->hypervisor_bin); // Load reset binary into memory - reset->loadSections(&functionalPort, SparcISA::LoadAddrMask); + reset->setTextBase(params()->reset_addr); + reset->loadSections(&funcRomPort); // Load the openboot binary - openboot->loadSections(&functionalPort, SparcISA::LoadAddrMask); + openboot->setTextBase(params()->openboot_addr); + openboot->loadSections(&funcRomPort); // Load the hypervisor binary - hypervisor->loadSections(&functionalPort, SparcISA::LoadAddrMask); + hypervisor->setTextBase(params()->hypervisor_addr); + hypervisor->loadSections(&funcRomPort); // load symbols if (!reset->loadGlobalSymbols(resetSymtab)) @@ -141,8 +148,13 @@ SparcSystem::unserialize(Checkpoint *cp, const std::string §ion) BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem) SimObjectParam physmem; + SimObjectParam rom; SimpleEnumParam mem_mode; + Param reset_addr; + Param hypervisor_addr; + Param openboot_addr; + Param kernel; Param reset_bin; Param hypervisor_bin; @@ -150,8 +162,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem) Param boot_cpu_frequency; Param boot_osflags; - Param system_type; - Param system_rev; Param readfile; Param init_param; @@ -160,8 +170,14 @@ END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem) BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem) INIT_PARAM(physmem, "phsyical memory"), + INIT_PARAM(rom, "ROM for boot code"), INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)", System::MemoryModeStrings), + + INIT_PARAM(reset_addr, "Address that reset should be loaded at"), + INIT_PARAM(hypervisor_addr, "Address that hypervisor should be loaded at"), + INIT_PARAM(openboot_addr, "Address that openboot should be loaded at"), + INIT_PARAM(kernel, "file that contains the kernel code"), INIT_PARAM(reset_bin, "file that contains the reset code"), INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"), @@ -169,8 +185,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem) INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", "a"), - INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34), - INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10), INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0) @@ -182,16 +196,18 @@ CREATE_SIM_OBJECT(SparcSystem) p->name = getInstanceName(); p->boot_cpu_frequency = boot_cpu_frequency; p->physmem = physmem; + p->rom = rom; p->mem_mode = mem_mode; p->kernel_path = kernel; + p->reset_addr = reset_addr; + p->hypervisor_addr = hypervisor_addr; + p->openboot_addr = openboot_addr; p->reset_bin = reset_bin; p->hypervisor_bin = hypervisor_bin; p->openboot_bin = openboot_bin; p->boot_osflags = boot_osflags; p->init_param = init_param; p->readfile = readfile; - p->system_type = system_type; - p->system_rev = system_rev; return new SparcSystem(p); } diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh index 0b79eda38..9cf3bb568 100644 --- a/src/arch/sparc/system.hh +++ b/src/arch/sparc/system.hh @@ -45,12 +45,14 @@ class SparcSystem : public System public: struct Params : public System::Params { + PhysicalMemory *rom; + Addr reset_addr; + Addr hypervisor_addr; + Addr openboot_addr; std::string reset_bin; std::string hypervisor_bin; std::string openboot_bin; std::string boot_osflags; - uint64_t system_type; - uint64_t system_rev; }; SparcSystem(Params *p); @@ -87,6 +89,9 @@ class SparcSystem : public System /** System Tick for syncronized tick across all cpus. */ Tick sysTick; + /** functional port to ROM */ + FunctionalPort funcRomPort; + protected: const Params *params() const { return (const Params *)_params; } -- cgit v1.2.3 From 50462c15aafc4ea076fb4bce69abe9cc32c33788 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 9 Nov 2006 19:24:35 -0500 Subject: Fix a couple uninitialized variables. --HG-- extra : convert_revision : d17d28a9520524e5f56bd79beb9b2be6ce76a22f --- src/arch/sparc/faults.cc | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index e895c02db..57ee040f1 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -493,21 +493,22 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) void getREDVector(Addr & PC, Addr & NPC) { + //XXX The following constant might belong in a header file. const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL; PC = RSTVAddr | 0xA0; NPC = PC + sizeof(MachInst); } -void getHyperVector(Addr & PC, Addr & NPC, MiscReg TT) +void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT) { - Addr HTBA ; + Addr HTBA = tc->readMiscReg(MISCREG_HTBA); PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14)); NPC = PC + sizeof(MachInst); } -void getPrivVector(Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL) +void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL) { - Addr TBA ; + Addr TBA = tc->readMiscReg(MISCREG_TBA); PC = (TBA & ~mask(15)) | (TL > 1 ? (1 << 14) : 0) | ((TT << 5) & mask(14)); @@ -556,17 +557,17 @@ void SparcFaultBase::invoke(ThreadContext * tc) { //guest_watchdog fault doNormalFault(tc, trapType(), true); - getHyperVector(PC, NPC, 2); + getHyperVector(tc, PC, NPC, 2); } else if(level == Hyperprivileged) { doNormalFault(tc, trapType(), true); - getHyperVector(PC, NPC, trapType()); + getHyperVector(tc, PC, NPC, trapType()); } else { doNormalFault(tc, trapType(), false); - getPrivVector(PC, NPC, trapType(), TL+1); + getPrivVector(tc, PC, NPC, trapType(), TL+1); } tc->setPC(PC); -- cgit v1.2.3 From 232c3f1b270aa04b924442bb6520c65c5a1414e1 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 9 Nov 2006 21:30:48 -0500 Subject: Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants. --HG-- extra : convert_revision : e4af5e2fb2a6953f8837ad9bda309b7d6fa7abfb --- src/arch/alpha/SConscript | 1 + src/arch/alpha/ev5.cc | 2 +- src/arch/alpha/isa/fp.isa | 2 +- src/arch/alpha/isa/main.isa | 11 +-- src/arch/alpha/isa_traits.hh | 8 +-- src/arch/alpha/locked_mem.hh | 12 ++-- src/arch/alpha/miscregfile.cc | 161 ++++++++++++++++++++++++++++++++++++++++++ src/arch/alpha/miscregfile.hh | 118 +++++++++++++++++++++++++++++++ src/arch/alpha/regfile.hh | 56 +-------------- src/arch/sparc/miscregfile.hh | 83 ++++++++++------------ 10 files changed, 332 insertions(+), 122 deletions(-) create mode 100644 src/arch/alpha/miscregfile.cc create mode 100644 src/arch/alpha/miscregfile.hh (limited to 'src/arch') diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 3947ec23a..d9c9765a1 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -49,6 +49,7 @@ Import('env') base_sources = Split(''' faults.cc isa_traits.cc + miscregfile.cc ''') # Full-system sources diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 59f9d2fb5..3d71fbda5 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -557,7 +557,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) void AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) { - for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { + for (int i = 0; i < NumInternalProcRegs; ++i) { dest->setMiscReg(i, src->readMiscReg(i)); } } diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa index 103f85775..3b5575f62 100644 --- a/src/arch/alpha/isa/fp.isa +++ b/src/arch/alpha/isa/fp.isa @@ -229,7 +229,7 @@ def template FloatingPointExecute {{ %(code)s; } else { fesetround(getC99RoundingMode( - xc->readMiscReg(AlphaISA::Fpcr_DepTag))); + xc->readMiscReg(AlphaISA::MISCREG_FPCR))); %(code)s; fesetround(FE_TONEAREST); } diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 06d3e8243..6e65cf9d3 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -184,9 +184,9 @@ def operands {{ 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), - 'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1), - 'FPCR': ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1), - 'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1), + 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), + 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), + 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), # The next two are hacks for non-full-system call-pal emulation 'R0': ('IntReg', 'uq', '0', None, 1), 'R16': ('IntReg', 'uq', '16', None, 1), @@ -216,11 +216,6 @@ output header {{ /// live here and not in the AlphaISA namespace. enum DependenceTags { FP_Base_DepTag = AlphaISA::FP_Base_DepTag, - Fpcr_DepTag = AlphaISA::Fpcr_DepTag, - Uniq_DepTag = AlphaISA::Uniq_DepTag, - Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag, - Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag, - IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag }; /// Constructor. diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index a919a4a1f..3759b022b 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -50,13 +50,7 @@ namespace AlphaISA // 0..31 are the integer regs 0..31 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) FP_Base_DepTag = 40, - Ctrl_Base_DepTag = 72, - Fpcr_DepTag = 72, // floating point control register - Uniq_DepTag = 73, - Lock_Flag_DepTag = 74, - Lock_Addr_DepTag = 75, - Intr_Flag_DepTag = 76, - IPR_Base_DepTag = 77 + Ctrl_Base_DepTag = 72 }; StaticInstPtr decodeInst(ExtMachInst); diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh index 368ea2895..52fe24173 100644 --- a/src/arch/alpha/locked_mem.hh +++ b/src/arch/alpha/locked_mem.hh @@ -37,7 +37,7 @@ * ISA-specific helper functions for locked memory accesses. */ -#include "arch/isa_traits.hh" +#include "arch/alpha/miscregfile.hh" #include "base/misc.hh" #include "mem/request.hh" @@ -48,8 +48,8 @@ template inline void handleLockedRead(XC *xc, Request *req) { - xc->setMiscReg(Lock_Addr_DepTag, req->getPaddr() & ~0xf); - xc->setMiscReg(Lock_Flag_DepTag, true); + xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); + xc->setMiscReg(MISCREG_LOCKFLAG, true); } @@ -63,13 +63,13 @@ handleLockedWrite(XC *xc, Request *req) req->setScResult(2); } else { // standard store conditional - bool lock_flag = xc->readMiscReg(Lock_Flag_DepTag); - Addr lock_addr = xc->readMiscReg(Lock_Addr_DepTag); + bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); + Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { // Lock flag not set or addr mismatch in CPU; // don't even bother sending to memory system req->setScResult(0); - xc->setMiscReg(Lock_Flag_DepTag, false); + xc->setMiscReg(MISCREG_LOCKFLAG, false); // the rest of this code is not architectural; // it's just a debugging aid to help detect // livelock by warning on long sequences of failed diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc new file mode 100644 index 000000000..4cf57a690 --- /dev/null +++ b/src/arch/alpha/miscregfile.cc @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + * Kevin Lim + */ + +#include "arch/alpha/miscregfile.hh" +#include "base/misc.hh" + +namespace AlphaISA +{ + + void + MiscRegFile::serialize(std::ostream &os) + { + SERIALIZE_SCALAR(fpcr); + SERIALIZE_SCALAR(uniq); + SERIALIZE_SCALAR(lock_flag); + SERIALIZE_SCALAR(lock_addr); +#if FULL_SYSTEM + SERIALIZE_ARRAY(ipr, NumInternalProcRegs); +#endif + } + + void + MiscRegFile::unserialize(Checkpoint *cp, const std::string §ion) + { + UNSERIALIZE_SCALAR(fpcr); + UNSERIALIZE_SCALAR(uniq); + UNSERIALIZE_SCALAR(lock_flag); + UNSERIALIZE_SCALAR(lock_addr); +#if FULL_SYSTEM + UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); +#endif + } + + MiscReg + MiscRegFile::readReg(int misc_reg) + { + switch(misc_reg) { + case MISCREG_FPCR: + return fpcr; + case MISCREG_UNIQ: + return uniq; + case MISCREG_LOCKFLAG: + return lock_flag; + case MISCREG_LOCKADDR: + return lock_addr; + case MISCREG_INTR: + return intr_flag; +#if FULL_SYSTEM + default: + assert(misc_reg < NumInternalProcRegs); + return ipr[misc_reg]; +#else + default: + panic("Attempt to read an invalid misc register!"); + return 0; +#endif + } + } + + MiscReg + MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc) + { +#if FULL_SYSTEM + return readIpr(misc_reg, tc); +#else + panic("No faulting misc regs in SE mode!"); + return 0; +#endif + } + + void + MiscRegFile::setReg(int misc_reg, const MiscReg &val) + { + switch(misc_reg) { + case MISCREG_FPCR: + fpcr = val; + return; + case MISCREG_UNIQ: + uniq = val; + return; + case MISCREG_LOCKFLAG: + lock_flag = val; + return; + case MISCREG_LOCKADDR: + lock_addr = val; + return; + case MISCREG_INTR: + intr_flag = val; + return; +#if FULL_SYSTEM + default: + assert(misc_reg < NumInternalProcRegs); + ipr[misc_reg] = val; + return; +#else + default: + panic("Attempt to write to an invalid misc register!"); +#endif + } + } + + void + MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val, + ThreadContext *tc) + { +#if FULL_SYSTEM + switch(misc_reg) { + case MISCREG_FPCR: + fpcr = val; + return; + case MISCREG_UNIQ: + uniq = val; + return; + case MISCREG_LOCKFLAG: + lock_flag = val; + return; + case MISCREG_LOCKADDR: + lock_addr = val; + return; + case MISCREG_INTR: + intr_flag = val; + return; + default: + return setIpr(misc_reg, val, tc); + } +#else + //panic("No registers with side effects in SE mode!"); + return; +#endif + } + +} diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh new file mode 100644 index 000000000..85cb054bb --- /dev/null +++ b/src/arch/alpha/miscregfile.hh @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + */ + +#ifndef __ARCH_ALPHA_MISCREGFILE_HH__ +#define __ARCH_ALPHA_MISCREGFILE_HH__ + +#include "arch/alpha/ipr.hh" +#include "arch/alpha/types.hh" +#include "config/full_system.hh" +#include "sim/host.hh" +#include "sim/serialize.hh" + +#include + +class Checkpoint; +class ThreadContext; + +namespace AlphaISA +{ + enum MiscRegIndex + { + MISCREG_FPCR = NumInternalProcRegs, + MISCREG_UNIQ, + MISCREG_LOCKFLAG, + MISCREG_LOCKADDR, + MISCREG_INTR + }; + + class MiscRegFile { + protected: + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + int intr_flag; + + public: + MiscRegFile() + { +#if FULL_SYSTEM + initializeIprTable(); +#endif + } + + MiscReg readReg(int misc_reg); + + MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc); + + //These functions should be removed once the simplescalar cpu model + //has been replaced. + int getInstAsid(); + int getDataAsid(); + + void setReg(int misc_reg, const MiscReg &val); + + void setRegWithEffect(int misc_reg, const MiscReg &val, + ThreadContext *tc); + + void clear() + { + fpcr = uniq = 0; + lock_flag = 0; + lock_addr = 0; + intr_flag = 0; + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); +#if FULL_SYSTEM + protected: + typedef uint64_t InternalProcReg; + + InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs + + private: + InternalProcReg readIpr(int idx, ThreadContext *tc); + + void setIpr(int idx, InternalProcReg val, ThreadContext *tc); +#endif + friend class RegFile; + }; + +#if FULL_SYSTEM + void copyIprs(ThreadContext *src, ThreadContext *dest); +#endif + +} + +#endif diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index e806adbcb..af28f6c6f 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -33,6 +33,7 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/ipr.hh" +#include "arch/alpha/miscregfile.hh" #include "arch/alpha/types.hh" #include "sim/faults.hh" @@ -104,61 +105,6 @@ namespace AlphaISA { bzero(d, sizeof(d)); } }; - class MiscRegFile { - protected: - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - int intr_flag; - - public: - MiscRegFile() - { -#if FULL_SYSTEM - initializeIprTable(); -#endif - } - - MiscReg readReg(int misc_reg); - - MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc); - - //These functions should be removed once the simplescalar cpu model - //has been replaced. - int getInstAsid(); - int getDataAsid(); - - void setReg(int misc_reg, const MiscReg &val); - - void setRegWithEffect(int misc_reg, const MiscReg &val, - ThreadContext *tc); - - void clear() - { - fpcr = uniq = 0; - lock_flag = 0; - lock_addr = 0; - intr_flag = 0; - } - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); -#if FULL_SYSTEM - protected: - typedef uint64_t InternalProcReg; - - InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs - - private: - InternalProcReg readIpr(int idx, ThreadContext *tc); - - void setIpr(int idx, InternalProcReg val, ThreadContext *tc); -#endif - friend class RegFile; - }; - class RegFile { protected: diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index 0e424dbd2..6d624787d 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -46,59 +46,54 @@ namespace SparcISA //These functions map register indices to names std::string getMiscRegName(RegIndex); - const int AsrStart = 0; - const int PrStart = 32; - const int HprStart = 64; - const int MiscStart = 96; - enum MiscRegIndex { /** Ancillary State Registers */ - MISCREG_Y = AsrStart + 0, - MISCREG_CCR = AsrStart + 2, - MISCREG_ASI = AsrStart + 3, - MISCREG_TICK = AsrStart + 4, - MISCREG_FPRS = AsrStart + 6, - MISCREG_PCR = AsrStart + 16, - MISCREG_PIC = AsrStart + 17, - MISCREG_GSR = AsrStart + 19, - MISCREG_SOFTINT_SET = AsrStart + 20, - MISCREG_SOFTINT_CLR = AsrStart + 21, - MISCREG_SOFTINT = AsrStart + 22, - MISCREG_TICK_CMPR = AsrStart + 23, - MISCREG_STICK = AsrStart + 24, - MISCREG_STICK_CMPR = AsrStart + 25, + MISCREG_Y, + MISCREG_CCR, + MISCREG_ASI, + MISCREG_TICK, + MISCREG_FPRS, + MISCREG_PCR, + MISCREG_PIC, + MISCREG_GSR, + MISCREG_SOFTINT_SET, + MISCREG_SOFTINT_CLR, + MISCREG_SOFTINT, + MISCREG_TICK_CMPR, + MISCREG_STICK, + MISCREG_STICK_CMPR, /** Privilged Registers */ - MISCREG_TPC = PrStart + 0, - MISCREG_TNPC = PrStart + 1, - MISCREG_TSTATE = PrStart + 2, - MISCREG_TT = PrStart + 3, - MISCREG_PRIVTICK = PrStart + 4, - MISCREG_TBA = PrStart + 5, - MISCREG_PSTATE = PrStart + 6, - MISCREG_TL = PrStart + 7, - MISCREG_PIL = PrStart + 8, - MISCREG_CWP = PrStart + 9, - MISCREG_CANSAVE = PrStart + 10, - MISCREG_CANRESTORE = PrStart + 11, - MISCREG_CLEANWIN = PrStart + 12, - MISCREG_OTHERWIN = PrStart + 13, - MISCREG_WSTATE = PrStart + 14, - MISCREG_GL = PrStart + 16, + MISCREG_TPC, + MISCREG_TNPC, + MISCREG_TSTATE, + MISCREG_TT, + MISCREG_PRIVTICK, + MISCREG_TBA, + MISCREG_PSTATE, + MISCREG_TL, + MISCREG_PIL, + MISCREG_CWP, + MISCREG_CANSAVE, + MISCREG_CANRESTORE, + MISCREG_CLEANWIN, + MISCREG_OTHERWIN, + MISCREG_WSTATE, + MISCREG_GL, /** Hyper privileged registers */ - MISCREG_HPSTATE = HprStart + 0, - MISCREG_HTSTATE = HprStart + 1, - MISCREG_HINTP = HprStart + 3, - MISCREG_HTBA = HprStart + 5, - MISCREG_HVER = HprStart + 6, - MISCREG_STRAND_STS_REG = HprStart + 16, - MISCREG_HSTICK_CMPR = HprStart + 31, + MISCREG_HPSTATE, + MISCREG_HTSTATE, + MISCREG_HINTP, + MISCREG_HTBA, + MISCREG_HVER, + MISCREG_STRAND_STS_REG, + MISCREG_HSTICK_CMPR, /** Floating Point Status Register */ - MISCREG_FSR = MiscStart + 0 - + MISCREG_FSR, + NumMiscRegs }; // The control registers, broken out into fields -- cgit v1.2.3 From 4aea5deccb948035459583d811837cb6affd1c07 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Nov 2006 04:02:39 -0500 Subject: Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host. --HG-- extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d --- src/arch/sparc/isa/decoder.isa | 197 ++++++++++++++++++++++++++++---- src/arch/sparc/isa/formats/priv.isa | 24 +++- src/arch/sparc/isa/includes.isa | 1 + src/arch/sparc/isa/operands.isa | 50 +++++--- src/arch/sparc/miscregfile.cc | 41 ++++--- src/arch/sparc/miscregfile.hh | 222 ++++-------------------------------- 6 files changed, 271 insertions(+), 264 deletions(-) (limited to 'src/arch') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index a5f43367d..4f3ea7810 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -346,22 +346,93 @@ decode OP default Unknown::unknown() 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); } - // XXX might want a format rdipr thing here 0x28: decode RS1 { - 0xF: decode I { + 0x00: NoPriv::rdy({{Rd = Y;}}); + //1 should cause an illegal instruction exception + 0x02: NoPriv::rdccr({{Rd = Ccr;}}); + 0x03: NoPriv::rdasi({{Rd = Asi;}}); + 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); + 0x05: NoPriv::rdpc({{ + if(Pstate<3:>) + Rd = (xc->readPC())<31:0>; + else + Rd = xc->readPC();}}); + 0x06: NoPriv::rdfprs({{ + //Wait for all fpops to finish. + Rd = Fprs; + }}); + //7-14 should cause an illegal instruction exception + 0x0F: decode I { 0x0: Nop::stbar({{/*stuff*/}}); 0x1: Nop::membar({{/*stuff*/}}); } - default: rdasr({{ - Rd = xc->readMiscRegWithEffect(RS1 + AsrStart); + 0x10: Priv::rdpcr({{Rd = Pcr;}}); + 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); + //0x12 should cause an illegal instruction exception + 0x13: NoPriv::rdgsr({{ + if(Fprs<2:> == 0 || Pstate<4:> == 0) + Rd = Gsr; + else + fault = new FpDisabled; }}); + //0x14-0x15 should cause an illegal instruction exception + 0x16: Priv::rdsoftint({{Rd = Softint;}}); + 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); + 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); + 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); + //0x1A-0x1F should cause an illegal instruction exception + } + 0x29: decode RS1 { + 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); + 0x01: HPriv::rdhprhtstate({{ + if(Tl == 0) + return new IllegalInstruction; + Rd = Htstate; + }}); + //0x02 should cause an illegal instruction exception + 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); + //0x04 should cause an illegal instruction exception + 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); + 0x06: HPriv::rdhprhver({{Rd = Hver;}}); + //0x07-0x1E should cause an illegal instruction exception + 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); + } + 0x2A: decode RS1 { + 0x00: Priv::rdprtpc({{ + if(Tl == 0) + return new IllegalInstruction; + Rd = Tpc; + }}); + 0x01: Priv::rdprtnpc({{ + if(Tl == 0) + return new IllegalInstruction; + Rd = Tnpc; + }}); + 0x02: Priv::rdprtstate({{ + if(Tl == 0) + return new IllegalInstruction; + Rd = Tstate; + }}); + 0x03: Priv::rdprtt({{ + if(Tl == 0) + return new IllegalInstruction; + Rd = Tt; + }}); + 0x04: Priv::rdprtick({{Rd = Tick;}}); + 0x05: Priv::rdprtba({{Rd = Tba;}}); + 0x06: Priv::rdprpstate({{Rd = Pstate;}}); + 0x07: Priv::rdprtl({{Rd = Tl;}}); + 0x08: Priv::rdprpil({{Rd = Pil;}}); + 0x09: Priv::rdprcwp({{Rd = Cwp;}}); + 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); + 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); + 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); + 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); + 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); + //0x0F should cause an illegal instruction exception + 0x10: Priv::rdprgl({{Rd = Gl;}}); + //0x11-0x1F should cause an illegal instruction exception } - 0x29: HPriv::rdhpr({{ - Rd = xc->readMiscRegWithEffect(RS1 + HprStart); - }}); - 0x2A: Priv::rdpr({{ - Rd = xc->readMiscRegWithEffect(RS1 + PrStart); - }}); 0x2B: BasicOperate::flushw({{ if(NWindows - 2 - Cansave == 0) { @@ -417,9 +488,35 @@ decode OP default Unknown::unknown() 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); } - 0x30: wrasr({{ - xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); - }}); + 0x30: decode RD { + 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}}); + //0x01 should cause an illegal instruction exception + 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); + 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}}); + //0x04-0x05 should cause an illegal instruction exception + 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); + //0x07-0x0E should cause an illegal instruction exception + 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); + 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); + 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); + //0x12 should cause an illegal instruction exception + 0x13: NoPriv::wrgsr({{ + if(Fprs<2:> == 0 || Pstate<4:> == 0) + return new FpDisabled; + Gsr = Rs1 ^ Rs2_or_imm13; + }}); + 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); + 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); + 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); + 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); + 0x18: NoPriv::wrstick({{ + if(!Hpstate<2:>) + return new IllegalInstruction; + Stick = Rs1 ^ Rs2_or_imm13; + }}); + 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); + //0x1A-0x1F should cause an illegal instruction exception + } 0x31: decode FCN { 0x0: Priv::saved({{ assert(Cansave < NWindows - 2); @@ -440,16 +537,70 @@ decode OP default Unknown::unknown() Otherwin = Otherwin - 1; }}); } - 0x32: Priv::wrpr({{ - // XXX Need to protect with format that traps non-priv - // access - xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); - }}); - 0x33: HPriv::wrhpr({{ - // XXX Need to protect with format that traps non-priv/priv - // access - xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); - }}); + 0x32: decode RD { + 0x00: Priv::wrprtpc({{ + if(Tl == 0) + return new IllegalInstruction; + else + Tpc = Rs1 ^ Rs2_or_imm13; + }}); + 0x01: Priv::wrprtnpc({{ + if(Tl == 0) + return new IllegalInstruction; + else + Tnpc = Rs1 ^ Rs2_or_imm13; + }}); + 0x02: Priv::wrprtstate({{ + if(Tl == 0) + return new IllegalInstruction; + else + Tstate = Rs1 ^ Rs2_or_imm13; + }}); + 0x03: Priv::wrprtt({{ + if(Tl == 0) + return new IllegalInstruction; + else + Tt = Rs1 ^ Rs2_or_imm13; + }}); + 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); + 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); + 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); + 0x07: Priv::wrprtl({{ + if(Pstate<2:> && !Hpstate<2:>) + Tl = std::min(Rs1 ^ Rs2_or_imm13, MaxPTL); + else + Tl = std::min(Rs1 ^ Rs2_or_imm13, MaxTL); + }}); + 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); + 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); + 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); + 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); + 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); + 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); + 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); + //0x0F should cause an illegal instruction exception + 0x10: Priv::wrprgl({{ + if(Pstate<2:> && !Hpstate<2:>) + Gl = std::min(Rs1 ^ Rs2_or_imm13, MaxPGL); + else + Gl = std::min(Rs1 ^ Rs2_or_imm13, MaxGL); + }}); + //0x11-0x1F should cause an illegal instruction exception + } + 0x33: decode RD { + 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); + 0x01: HPriv::wrhprhtstate({{ + if(Tl == 0) + return new IllegalInstruction; + Htstate = Rs1 ^ Rs2_or_imm13; + }}); + //0x02 should cause an illegal instruction exception + 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); + //0x04 should cause an illegal instruction exception + 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); + //0x06-0x01D should cause an illegal instruction exception + 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); + } 0x34: decode OPF{ format BasicOperate{ 0x01: fmovs({{ diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 04c67d332..55bf968f4 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -119,18 +119,34 @@ let {{ return (header_output, decoder_output, exec_output, decode_block) }}; -// Primary format for integer operate instructions: def format Priv(code, *opt_flags) {{ - checkCode = "!(Pstate<2:2> || Hpstate<2:2>)" + checkCode = "!(Pstate<2:> || Hpstate<2:>)" (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags + ('IprAccessOp',)) + checkCode, name, Name, opt_flags) +}}; + +def format NoPriv(code, *opt_flags) {{ + #Instructions which use this format don't really check for + #any particular mode, but the disassembly is performed + #using the control registers actual name + checkCode = "false" + (header_output, decoder_output, + exec_output, decode_block) = doPrivFormat(code, + checkCode, name, Name, opt_flags) +}}; + +def format PrivCheck(code, extraCheckCode, *opt_flags) {{ + checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCheckCode + (header_output, decoder_output, + exec_output, decode_block) = doPrivFormat(code, + checkCode, name, Name, opt_flags) }}; def format HPriv(code, *opt_flags) {{ checkCode = "!Hpstate<2:2>" (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags + ('IprAccessOp',)) + checkCode, name, Name, opt_flags) }}; diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index a324756ec..624afb693 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -54,6 +54,7 @@ output decoder {{ #if defined(linux) #include #endif +#include using namespace SparcISA; }}; diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 80b499b91..caee20b0c 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -80,8 +80,6 @@ def operands {{ 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), - #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), - #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 'R0': ('IntReg', 'udw', '0', None, 6), 'R1': ('IntReg', 'udw', '1', None, 7), 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), @@ -91,24 +89,42 @@ def operands {{ 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), + 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), + 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), + 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), + 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46), + 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), + 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), + 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), + 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), + 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), + 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), - 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), - 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), - 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), - 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), - 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47), - 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48), + 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), + 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), + 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), + 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), + 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), + 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), + 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), + 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), + 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), + 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62), + 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), + 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), + 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), + 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), + 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), + 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), - 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49), - 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50), - 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51), - 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52), - 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53), - 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54), - 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55), + 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), + 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), + 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), + 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), + 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), + 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), - 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56), - 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57), + 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80), # Mem gets a large number so it's always last 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 217fba0bd..714c9bdab 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -30,6 +30,7 @@ */ #include "arch/sparc/miscregfile.hh" +#include "base/bitfield.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/base.hh" @@ -78,8 +79,9 @@ MiscReg MiscRegFile::readReg(int miscReg) case MISCREG_TICK: return tick; case MISCREG_PCR: + panic("PCR not implemented\n"); case MISCREG_PIC: - panic("ASR number %d not implemented\n", miscReg - AsrStart); + panic("PIC not implemented\n"); case MISCREG_GSR: return gsr; case MISCREG_SOFTINT: @@ -154,8 +156,8 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) switch (miscReg) { case MISCREG_TICK: case MISCREG_PRIVTICK: - return tc->getCpuPtr()->curCycle() - tickFields.counter | - tickFields.npt << 63; + return tc->getCpuPtr()->curCycle() - (tick & mask(63)) | + (tick & ~(mask(63))) << 63; case MISCREG_FPRS: panic("FPU not implemented\n"); case MISCREG_PCR: @@ -171,7 +173,7 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) SparcSystem *sys; sys = dynamic_cast(tc->getSystemPtr()); assert(sys != NULL); - return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; + return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); #endif case MISCREG_HVER: return NWindows | MaxTL << 8 | MaxGL << 16; @@ -198,8 +200,9 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) tick = val; break; case MISCREG_PCR: + panic("PCR not implemented\n"); case MISCREG_PIC: - panic("ASR number %d not implemented\n", miscReg - AsrStart); + panic("PIC not implemented\n"); case MISCREG_GSR: gsr = val; break; @@ -303,12 +306,12 @@ inline void MiscRegFile::setImplicitAsis() if(tl == 0) { implicitInstAsi = implicitDataAsi = - pstateFields.cle ? ASI_PRIMARY_LITTLE : ASI_PRIMARY; + (pstate & (1 << 9)) ? ASI_PRIMARY_LITTLE : ASI_PRIMARY; } else if(tl <= MaxPTL) { implicitInstAsi = ASI_NUCLEUS; - implicitDataAsi = pstateFields.cle ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS; + implicitDataAsi = (pstate & (1 << 9)) ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS; } else { @@ -328,8 +331,8 @@ void MiscRegFile::setRegWithEffect(int miscReg, #endif switch (miscReg) { case MISCREG_TICK: - tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64; - tickFields.npt = val & Bit64 ? 1 : 0; + tick = tc->getCpuPtr()->curCycle() - val & ~Bit64; + tick |= val & Bit64; break; case MISCREG_FPRS: //Configure the fpu based on the fprs @@ -369,10 +372,10 @@ void MiscRegFile::setRegWithEffect(int miscReg, if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); setReg(miscReg, val); - if (tick_cmprFields.int_dis && tickCompare->scheduled()) + if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) tickCompare->deschedule(); - time = tick_cmprFields.tick_cmpr - tickFields.counter; - if (!tick_cmprFields.int_dis && time > 0) + time = (tick_cmpr & mask(63)) - (tick & mask(63)); + if (!(tick_cmpr & ~mask(63)) && time > 0) tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); break; #endif @@ -390,17 +393,17 @@ void MiscRegFile::setRegWithEffect(int miscReg, sys = dynamic_cast(tc->getSystemPtr()); assert(sys != NULL); sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; - stickFields.npt = val & Bit64 ? 1 : 0; + stick |= val & Bit64; break; case MISCREG_STICK_CMPR: if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); sys = dynamic_cast(tc->getSystemPtr()); assert(sys != NULL); - if (stick_cmprFields.int_dis && sTickCompare->scheduled()) + if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) sTickCompare->deschedule(); - time = stick_cmprFields.tick_cmpr - sys->sysTick; - if (!stick_cmprFields.int_dis && time > 0) + time = (stick_cmpr & mask(63)) - sys->sysTick; + if (!(stick_cmpr & ~mask(63)) && time > 0) sTickCompare->schedule(time * Clock::Int::ns); break; case MISCREG_HSTICK_CMPR: @@ -408,10 +411,10 @@ void MiscRegFile::setRegWithEffect(int miscReg, hSTickCompare = new HSTickCompareEvent(this, tc); sys = dynamic_cast(tc->getSystemPtr()); assert(sys != NULL); - if (hstick_cmprFields.int_dis && hSTickCompare->scheduled()) + if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) hSTickCompare->deschedule(); - int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; - if (!hstick_cmprFields.int_dis && time > 0) + int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick; + if (!(hstick_cmpr & ~mask(63)) && time > 0) hSTickCompare->schedule(time * Clock::Int::ns); break; #endif diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index 6d624787d..f74943256 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -92,8 +92,7 @@ namespace SparcISA MISCREG_HSTICK_CMPR, /** Floating Point Status Register */ - MISCREG_FSR, - NumMiscRegs + MISCREG_FSR }; // The control registers, broken out into fields @@ -102,93 +101,16 @@ namespace SparcISA private: /* ASR Registers */ - union { - uint64_t y; // Y (used in obsolete multiplication) - struct { - uint64_t value:32; // The actual value stored in y - uint64_t :32; // reserved bits - } yFields; - }; - union { - uint8_t ccr; // Condition Code Register - struct { - union { - uint8_t icc:4; // 32-bit condition codes - struct { - uint8_t c:1; // Carry - uint8_t v:1; // Overflow - uint8_t z:1; // Zero - uint8_t n:1; // Negative - } iccFields; - }; - union { - uint8_t xcc:4; // 64-bit condition codes - struct { - uint8_t c:1; // Carry - uint8_t v:1; // Overflow - uint8_t z:1; // Zero - uint8_t n:1; // Negative - } xccFields; - }; - } ccrFields; - }; + uint64_t y; // Y (used in obsolete multiplication) + uint8_t ccr; // Condition Code Register uint8_t asi; // Address Space Identifier - union { - uint64_t tick; // Hardware clock-tick counter - struct { - int64_t counter:63; // Clock-tick count - uint64_t npt:1; // Non-priveleged trap - } tickFields; - }; - union { - uint8_t fprs; // Floating-Point Register State - struct { - uint8_t dl:1; // Dirty lower - uint8_t du:1; // Dirty upper - uint8_t fef:1; // FPRS enable floating-Point - } fprsFields; - }; - union { - uint64_t gsr; //General Status Register - struct { - uint64_t mask:32; - uint64_t :4; - uint64_t im:1; - uint64_t irnd:2; - uint64_t :17; - uint64_t scale:5; - uint64_t align:3; - } gsrFields; - }; - union { - uint64_t softint; - struct { - uint64_t tm:1; - uint64_t int_level:14; - uint64_t sm:1; - } softintFields; - }; - union { - uint64_t tick_cmpr; // Hardware tick compare registers - struct { - uint64_t tick_cmpr:63; // Clock-tick count - uint64_t int_dis:1; // Non-priveleged trap - } tick_cmprFields; - }; - union { - uint64_t stick; // Hardware clock-tick counter - struct { - int64_t :63; // Not used, storage in SparcSystem - uint64_t npt:1; // Non-priveleged trap - } stickFields; - }; - union { - uint64_t stick_cmpr; // Hardware tick compare registers - struct { - uint64_t tick_cmpr:63; // Clock-tick count - uint64_t int_dis:1; // Non-priveleged trap - } stick_cmprFields; - }; + uint64_t tick; // Hardware clock-tick counter + uint8_t fprs; // Floating-Point Register State + uint64_t gsr; // General Status Register + uint64_t softint; + uint64_t tick_cmpr; // Hardware tick compare registers + uint64_t stick; // Hardware clock-tick counter + uint64_t stick_cmpr; // Hardware tick compare registers /* Privileged Registers */ @@ -196,37 +118,12 @@ namespace SparcISA // previous trap level) uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from // previous trap level) - union { - uint64_t tstate[MaxTL]; // Trap State - struct { - //Values are from previous trap level - uint64_t cwp:5; // Current Window Pointer - uint64_t :3; // Reserved bits - uint64_t pstate:13; // Process State - uint64_t :3; // Reserved bits - uint64_t asi:8; // Address Space Identifier - uint64_t ccr:8; // Condition Code Register - uint64_t gl:8; // Global level - } tstateFields[MaxTL]; - }; + uint64_t tstate[MaxTL]; // Trap State uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured // on the previous level) uint64_t tba; // Trap Base Address - union { - uint16_t pstate; // Process State Register - struct { - uint16_t :1; // reserved - uint16_t ie:1; // Interrupt enable - uint16_t priv:1; // Privelege mode - uint16_t am:1; // Address mask - uint16_t pef:1; // PSTATE enable floating-point - uint16_t :1; // reserved2 - uint16_t mm:2; // Memory Model - uint16_t tle:1; // Trap little-endian - uint16_t cle:1; // Current little-endian - } pstateFields; - }; + uint16_t pstate; // Process State Register uint8_t tl; // Trap Level uint8_t pil; // Process Interrupt Register uint8_t cwp; // Current Window Pointer @@ -234,97 +131,20 @@ namespace SparcISA uint8_t canrestore; // Restorable windows uint8_t cleanwin; // Clean windows uint8_t otherwin; // Other windows - union { - uint8_t wstate; // Window State - struct { - uint8_t normal:3; // Bits TT<4:2> are set to on a normal - // register window trap - uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" - // register window trap - } wstateFields; - }; + uint8_t wstate; // Window State uint8_t gl; // Global level register - /** Hyperprivileged Registers */ - union { - uint64_t hpstate; // Hyperprivileged State Register - struct { - uint8_t tlz: 1; - uint8_t :1; - uint8_t hpriv:1; - uint8_t :2; - uint8_t red:1; - uint8_t :4; - uint8_t ibe:1; - uint8_t id:1; - } hpstateFields; - }; - - uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register + uint64_t hpstate; // Hyperprivileged State Register + uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register uint64_t hintp; - uint64_t htba; // Hyperprivileged Trap Base Address register - union { - uint64_t hstick_cmpr; // Hardware tick compare registers - struct { - uint64_t tick_cmpr:63; // Clock-tick count - uint64_t int_dis:1; // Non-priveleged trap - } hstick_cmprFields; - }; - - uint64_t strandStatusReg; // Per strand status register + uint64_t htba; // Hyperprivileged Trap Base Address register + uint64_t hstick_cmpr; // Hardware tick compare registers + uint64_t strandStatusReg;// Per strand status register /** Floating point misc registers. */ - union { - uint64_t fsr; // Floating-Point State Register - struct { - union { - uint64_t cexc:5; // Current excpetion - struct { - uint64_t nxc:1; // Inexact - uint64_t dzc:1; // Divide by zero - uint64_t ufc:1; // Underflow - uint64_t ofc:1; // Overflow - uint64_t nvc:1; // Invalid operand - } cexcFields; - }; - union { - uint64_t aexc:5; // Accrued exception - struct { - uint64_t nxc:1; // Inexact - uint64_t dzc:1; // Divide by zero - uint64_t ufc:1; // Underflow - uint64_t ofc:1; // Overflow - uint64_t nvc:1; // Invalid operand - } aexcFields; - }; - uint64_t fcc0:2; // Floating-Point condtion codes - uint64_t :1; // Reserved bits - uint64_t qne:1; // Deferred trap queue not empty - // with no queue, it should read 0 - uint64_t ftt:3; // Floating-Point trap type - uint64_t ver:3; // Version (of the FPU) - uint64_t :2; // Reserved bits - uint64_t ns:1; // Nonstandard floating point - union { - uint64_t tem:5; // Trap Enable Mask - struct { - uint64_t nxm:1; // Inexact - uint64_t dzm:1; // Divide by zero - uint64_t ufm:1; // Underflow - uint64_t ofm:1; // Overflow - uint64_t nvm:1; // Invalid operand - } temFields; - }; - uint64_t :2; // Reserved bits - uint64_t rd:2; // Rounding direction - uint64_t fcc1:2; // Floating-Point condition codes - uint64_t fcc2:2; // Floating-Point condition codes - uint64_t fcc3:2; // Floating-Point condition codes - uint64_t :26; // Reserved bits - } fsrFields; - }; + uint64_t fsr; // Floating-Point State Register ASI implicitInstAsi; ASI implicitDataAsi; @@ -386,8 +206,8 @@ namespace SparcISA protected: - bool isHyperPriv() { return hpstateFields.hpriv; } - bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; } + bool isHyperPriv() { return (hpstate & (1 << 2)); } + bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } bool isNonPriv() { return !isPriv(); } inline void setImplicitAsis(); }; -- cgit v1.2.3 From dc6af9fbf7bbbe29e431190867a2fed6fdcce8b5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Nov 2006 04:14:25 -0500 Subject: Set the ASI register to be something explicitly so that simulation is deterministic. --HG-- extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99 --- src/arch/sparc/process.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch') diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index a3b7dde7c..11a799ccb 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -29,6 +29,7 @@ * Ali Saidi */ +#include "arch/sparc/asi.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/process.hh" #include "base/loader/object_file.hh" @@ -105,6 +106,8 @@ SparcLiveProcess::startup() threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0); //Set the trap level to 0 threadContexts[0]->setMiscReg(MISCREG_TL, 0); + //Set the ASI register to something fixed + threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY); } m5_auxv_t buildAuxVect(int64_t type, int64_t val) -- cgit v1.2.3 From 71dc49c785b8623b82bf0d7b9df6085a3cd66dfa Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Nov 2006 04:33:41 -0500 Subject: The reset function of the MiscRegFile really resets it now. This function is called from the class's constructor. --HG-- extra : convert_revision : 4e7a40ffe0a9a71fd1b2b171d9c0dcac50e1a1fe --- src/arch/sparc/miscregfile.cc | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'src/arch') diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 714c9bdab..d52e3983f 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -29,6 +29,7 @@ * Ali Saidi */ +#include "arch/sparc/asi.hh" #include "arch/sparc/miscregfile.hh" #include "base/bitfield.hh" #include "base/trace.hh" @@ -63,6 +64,39 @@ string SparcISA::getMiscRegName(RegIndex index) void MiscRegFile::reset() { + y = 0; + ccr = 0; + asi = 0; + tick = 0; + fprs = 0; + gsr = 0; + softint = 0; + tick_cmpr = 0; + stick = 0; + stick_cmpr = 0; + memset(tpc, 0, sizeof(tpc)); + memset(tnpc, 0, sizeof(tnpc)); + memset(tstate, 0, sizeof(tstate)); + memset(tt, 0, sizeof(tt)); + pstate = 0; + tl = 0; + pil = 0; + cwp = 0; + cansave = 0; + canrestore = 0; + cleanwin = 0; + otherwin = 0; + wstate = 0; + gl = 0; + hpstate = 0; + memset(htstate, 0, sizeof(htstate)); + hintp = 0; + htba = 0; + hstick_cmpr = 0; + strandStatusReg = 0; + fsr = 0; + implicitInstAsi = ASI_PRIMARY; + implicitDataAsi = ASI_PRIMARY; } MiscReg MiscRegFile::readReg(int miscReg) -- cgit v1.2.3 From b4dfbf3aab700f4cc9c5638c2275c588a56778c8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Nov 2006 04:54:25 -0500 Subject: Split out alpha integer register file into it's own files. --HG-- extra : convert_revision : 164bdcec2860c5dca3f0f11d189781b88dd717cb --- src/arch/alpha/SConscript | 1 + src/arch/alpha/intregfile.cc | 65 +++++++++++++++++++++++++++++++++++++++ src/arch/alpha/intregfile.hh | 73 ++++++++++++++++++++++++++++++++++++++++++++ src/arch/alpha/isa_traits.hh | 4 --- src/arch/alpha/regfile.hh | 32 +------------------ 5 files changed, 140 insertions(+), 35 deletions(-) create mode 100644 src/arch/alpha/intregfile.cc create mode 100644 src/arch/alpha/intregfile.hh (limited to 'src/arch') diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index d9c9765a1..b0a725e7a 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -50,6 +50,7 @@ base_sources = Split(''' faults.cc isa_traits.cc miscregfile.cc + intregfile.cc ''') # Full-system sources diff --git a/src/arch/alpha/intregfile.cc b/src/arch/alpha/intregfile.cc new file mode 100644 index 000000000..0188cb2cd --- /dev/null +++ b/src/arch/alpha/intregfile.cc @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + * Kevin Lim + */ + +#include "arch/alpha/isa_traits.hh" +#include "arch/alpha/intregfile.hh" +#include "sim/serialize.hh" + +namespace AlphaISA +{ +#if FULL_SYSTEM + const int reg_redir[AlphaISA::NumIntRegs] = { + /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7, + /* 8 */ 32, 33, 34, 35, 36, 37, 38, 15, + /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23, + /* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 }; +#else + const int reg_redir[AlphaISA::NumIntRegs] = { + /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7, + /* 8 */ 8, 9, 10, 11, 12, 13, 14, 15, + /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23, + /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 }; +#endif + + void + IntRegFile::serialize(std::ostream &os) + { + SERIALIZE_ARRAY(regs, NumIntRegs); + } + + void + IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(regs, NumIntRegs); + } +} + diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh new file mode 100644 index 000000000..78f666345 --- /dev/null +++ b/src/arch/alpha/intregfile.hh @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + */ + +#ifndef __ARCH_ALPHA_INTREGFILE_HH__ +#define __ARCH_ALPHA_INTREGFILE_HH__ + +#include "arch/alpha/types.hh" + +#include +#include + +class Checkpoint; + +namespace AlphaISA +{ + // redirected register map, really only used for the full system case. + extern const int reg_redir[NumIntRegs]; + + class IntRegFile + { + protected: + IntReg regs[NumIntRegs]; + + public: + + IntReg readReg(int intReg) + { + return regs[intReg]; + } + + void setReg(int intReg, const IntReg &val) + { + regs[intReg] = val; + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + + void clear() + { bzero(regs, sizeof(regs)); } + }; +} + +#endif diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index 3759b022b..35d9ce843 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -114,7 +114,6 @@ namespace AlphaISA NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }; - // EV5 modes enum mode_type { @@ -181,9 +180,6 @@ namespace AlphaISA // Alpha UNOP (ldq_u r31,0(r0)) const ExtMachInst NoopMachInst = 0x2ffe0000; - // redirected register map, really only used for the full system case. - extern const int reg_redir[NumIntRegs]; - }; #endif // __ARCH_ALPHA_ISA_TRAITS_HH__ diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index af28f6c6f..091f0e2e6 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -32,7 +32,7 @@ #define __ARCH_ALPHA_REGFILE_HH__ #include "arch/alpha/isa_traits.hh" -#include "arch/alpha/ipr.hh" +#include "arch/alpha/intregfile.hh" #include "arch/alpha/miscregfile.hh" #include "arch/alpha/types.hh" #include "sim/faults.hh" @@ -62,32 +62,6 @@ namespace AlphaISA return ""; } - class IntRegFile - { - protected: - IntReg regs[NumIntRegs]; - - public: - - IntReg readReg(int intReg) - { - return regs[intReg]; - } - - Fault setReg(int intReg, const IntReg &val) - { - regs[intReg] = val; - return NoFault; - } - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - - void clear() - { bzero(regs, sizeof(regs)); } - }; - class FloatRegFile { public: @@ -249,10 +223,6 @@ namespace AlphaISA void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - -#if FULL_SYSTEM - void copyIprs(ThreadContext *src, ThreadContext *dest); -#endif } // namespace AlphaISA #endif -- cgit v1.2.3 From 9731fb3fd72ed2e8f5bf3423a33d45a5c35f636f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Nov 2006 05:29:05 -0500 Subject: Moved the Alpha float regfile into it's own regfile and got rid of constants.hh and isa_traits.cc --HG-- extra : convert_revision : 55afd7d21c276906520da375b3bbb563be420880 --- src/arch/alpha/SConscript | 14 +++--- src/arch/alpha/floatregfile.cc | 49 ++++++++++++++++++++ src/arch/alpha/floatregfile.hh | 63 +++++++++++++++++++++++++ src/arch/alpha/pagetable.cc | 63 +++++++++++++++++++++++++ src/arch/alpha/regfile.cc | 101 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 284 insertions(+), 6 deletions(-) create mode 100644 src/arch/alpha/floatregfile.cc create mode 100644 src/arch/alpha/floatregfile.hh create mode 100644 src/arch/alpha/pagetable.cc create mode 100644 src/arch/alpha/regfile.cc (limited to 'src/arch') diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index b0a725e7a..3cc5ec270 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -48,27 +48,29 @@ Import('env') # Base sources used by all configurations. base_sources = Split(''' faults.cc - isa_traits.cc - miscregfile.cc + floatregfile.cc intregfile.cc + miscregfile.cc + regfile.cc ''') # Full-system sources full_system_sources = Split(''' - tlb.cc arguments.cc ev5.cc + freebsd/system.cc idle_event.cc ipr.cc kernel_stats.cc + linux/system.cc osfpal.cc + pagetable.cc stacktrace.cc - vtophys.cc remote_gdb.cc system.cc - freebsd/system.cc - linux/system.cc + tlb.cc tru64/system.cc + vtophys.cc ''') diff --git a/src/arch/alpha/floatregfile.cc b/src/arch/alpha/floatregfile.cc new file mode 100644 index 000000000..512b0df95 --- /dev/null +++ b/src/arch/alpha/floatregfile.cc @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + * Kevin Lim + */ + +#include "arch/alpha/floatregfile.hh" +#include "sim/serialize.hh" + +namespace AlphaISA +{ + void + FloatRegFile::serialize(std::ostream &os) + { + SERIALIZE_ARRAY(q, NumFloatRegs); + } + + void + FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(q, NumFloatRegs); + } +} diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh new file mode 100644 index 000000000..6b394da03 --- /dev/null +++ b/src/arch/alpha/floatregfile.hh @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + */ + +#ifndef __ARCH_ALPHA_FLOATREGFILE_HH__ +#define __ARCH_ALPHA_FLOATREGFILE_HH__ + +#include "arch/alpha/isa_traits.hh" +#include "arch/alpha/types.hh" + +#include +#include + +class Checkpoint; + +namespace AlphaISA +{ + class FloatRegFile + { + public: + + union { + uint64_t q[NumFloatRegs]; // integer qword view + double d[NumFloatRegs]; // double-precision floating point view + }; + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + + void clear() + { bzero(d, sizeof(d)); } + }; +} + +#endif diff --git a/src/arch/alpha/pagetable.cc b/src/arch/alpha/pagetable.cc new file mode 100644 index 000000000..0c26ccbe3 --- /dev/null +++ b/src/arch/alpha/pagetable.cc @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/alpha/pagetable.hh" +#include "sim/serialize.hh" + +namespace AlphaISA +{ + void + PTE::serialize(std::ostream &os) + { + SERIALIZE_SCALAR(tag); + SERIALIZE_SCALAR(ppn); + SERIALIZE_SCALAR(xre); + SERIALIZE_SCALAR(xwe); + SERIALIZE_SCALAR(asn); + SERIALIZE_SCALAR(asma); + SERIALIZE_SCALAR(fonr); + SERIALIZE_SCALAR(fonw); + SERIALIZE_SCALAR(valid); + } + + void + PTE::unserialize(Checkpoint *cp, const std::string §ion) + { + UNSERIALIZE_SCALAR(tag); + UNSERIALIZE_SCALAR(ppn); + UNSERIALIZE_SCALAR(xre); + UNSERIALIZE_SCALAR(xwe); + UNSERIALIZE_SCALAR(asn); + UNSERIALIZE_SCALAR(asma); + UNSERIALIZE_SCALAR(fonr); + UNSERIALIZE_SCALAR(fonw); + UNSERIALIZE_SCALAR(valid); + } +} diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc new file mode 100644 index 000000000..92e1b07df --- /dev/null +++ b/src/arch/alpha/regfile.cc @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + * Kevin Lim + */ + +#include "arch/alpha/regfile.hh" +#include "cpu/thread_context.hh" + +namespace AlphaISA +{ + void + RegFile::serialize(std::ostream &os) + { + intRegFile.serialize(os); + floatRegFile.serialize(os); + miscRegFile.serialize(os); + SERIALIZE_SCALAR(pc); + SERIALIZE_SCALAR(npc); +#if FULL_SYSTEM + SERIALIZE_SCALAR(intrflag); +#endif + } + + void + RegFile::unserialize(Checkpoint *cp, const std::string §ion) + { + intRegFile.unserialize(cp, section); + floatRegFile.unserialize(cp, section); + miscRegFile.unserialize(cp, section); + UNSERIALIZE_SCALAR(pc); + UNSERIALIZE_SCALAR(npc); +#if FULL_SYSTEM + UNSERIALIZE_SCALAR(intrflag); +#endif + } + + void + copyRegs(ThreadContext *src, ThreadContext *dest) + { + // First loop through the integer registers. + for (int i = 0; i < NumIntRegs; ++i) { + dest->setIntReg(i, src->readIntReg(i)); + } + + // Then loop through the floating point registers. + for (int i = 0; i < TheISA::NumFloatRegs; ++i) { + dest->setFloatRegBits(i, src->readFloatRegBits(i)); + } + + // Copy misc. registers + copyMiscRegs(src, dest); + + // Lastly copy PC/NPC + dest->setPC(src->readPC()); + dest->setNextPC(src->readNextPC()); + } + + void + copyMiscRegs(ThreadContext *src, ThreadContext *dest) + { + dest->setMiscReg(AlphaISA::MISCREG_FPCR, + src->readMiscReg(AlphaISA::MISCREG_FPCR)); + dest->setMiscReg(AlphaISA::MISCREG_UNIQ, + src->readMiscReg(AlphaISA::MISCREG_UNIQ)); + dest->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, + src->readMiscReg(AlphaISA::MISCREG_LOCKFLAG)); + dest->setMiscReg(AlphaISA::MISCREG_LOCKADDR, + src->readMiscReg(AlphaISA::MISCREG_LOCKADDR)); + +#if FULL_SYSTEM + copyIprs(src, dest); +#endif + } +} -- cgit v1.2.3 From 9ef51f2dbaba88c10366d708f0ca872bb39064e4 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Nov 2006 05:49:16 -0500 Subject: Actually finished moving the register file stuff around. --HG-- extra : convert_revision : 786735ecea8ff480db6b3754ac5daa562938d988 --- src/arch/alpha/floatregfile.hh | 5 +++++ src/arch/alpha/intregfile.hh | 5 +++++ src/arch/alpha/miscregfile.hh | 5 +++++ src/arch/alpha/regfile.hh | 33 +-------------------------------- 4 files changed, 16 insertions(+), 32 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh index 6b394da03..d289f5785 100644 --- a/src/arch/alpha/floatregfile.hh +++ b/src/arch/alpha/floatregfile.hh @@ -42,6 +42,11 @@ class Checkpoint; namespace AlphaISA { + static inline std::string getFloatRegName(RegIndex) + { + return ""; + } + class FloatRegFile { public: diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh index 78f666345..0d65f69e0 100644 --- a/src/arch/alpha/intregfile.hh +++ b/src/arch/alpha/intregfile.hh @@ -41,6 +41,11 @@ class Checkpoint; namespace AlphaISA { + static inline std::string getIntRegName(RegIndex) + { + return ""; + } + // redirected register map, really only used for the full system case. extern const int reg_redir[NumIntRegs]; diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh index 85cb054bb..31b3e59b3 100644 --- a/src/arch/alpha/miscregfile.hh +++ b/src/arch/alpha/miscregfile.hh @@ -54,6 +54,11 @@ namespace AlphaISA MISCREG_INTR }; + static inline std::string getMiscRegName(RegIndex) + { + return ""; + } + class MiscRegFile { protected: uint64_t fpcr; // floating point condition codes diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 091f0e2e6..ff5830822 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -32,6 +32,7 @@ #define __ARCH_ALPHA_REGFILE_HH__ #include "arch/alpha/isa_traits.hh" +#include "arch/alpha/floatregfile.hh" #include "arch/alpha/intregfile.hh" #include "arch/alpha/miscregfile.hh" #include "arch/alpha/types.hh" @@ -47,38 +48,6 @@ class ThreadContext; namespace AlphaISA { - static inline std::string getIntRegName(RegIndex) - { - return ""; - } - - static inline std::string getFloatRegName(RegIndex) - { - return ""; - } - - static inline std::string getMiscRegName(RegIndex) - { - return ""; - } - - class FloatRegFile - { - public: - - union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - }; - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - - void clear() - { bzero(d, sizeof(d)); } - }; - class RegFile { protected: -- cgit v1.2.3