From cf846d5205c021a04ab1a8e830d9cb86be0bda6e Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 17 Jul 2007 15:28:48 -0700
Subject: Add in operand which holds the condition code bits of the flag
 register.

--HG--
extra : convert_revision : 416052f41fccc8286b3bdbe8d559512a761224f2
---
 src/arch/x86/isa/operands.isa | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/arch')

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index b2ac17d66..83df583ea 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -103,5 +103,6 @@ def operands {{
         'Index':         ('IntReg', 'uqw', 'index', 'IsInteger', 5),
         'Data':          ('IntReg', 'uqw', 'data', 'IsInteger', 6),
         'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
+        'ccFlagBits':       ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 }};
-- 
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