From d70c31437ab4309ba317c90189f1683c8e9e2730 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:06 -0500
Subject: ARM: Support instructions that set the GE bits when they write the
 condition codes.

---
 src/arch/arm/isa/insts/data.isa | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/arch')

diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 9de42807e..5d14f3b75 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -43,6 +43,10 @@ let {{
     decoder_output = ""
     exec_output = ""
 
+    calcGECode = '''
+        CondCodes = insertBits(CondCodes, 19, 16, resTemp);
+    '''
+
     calcQCode = '''
         CondCodes = CondCodes | ((resTemp & 1) << 27);
     '''
@@ -108,6 +112,8 @@ let {{
             negBit = 63
         if flagType == "saturate":
             immCcCode = calcQCode
+        elif flagType == "ge":
+            immCcCode = calcGECode
         else:
             immCcCode = calcCcCode % {
                 "icValue": secondOpRe.sub(immOp2, cCode[0]),
@@ -143,6 +149,8 @@ let {{
             negBit = 63
         if flagType == "saturate":
             regCcCode = calcQCode
+        elif flagType == "ge":
+            immCcCode = calcGECode
         else:
             regCcCode = calcCcCode % {
                 "icValue": secondOpRe.sub(regOp2, cCode[1]),
@@ -179,6 +187,8 @@ let {{
             negBit = 63
         if flagType == "saturate":
             regRegCcCode = calcQCode
+        elif flagType == "ge":
+            immCcCode = calcGECode
         else:
             regRegCcCode = calcCcCode % {
                 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
-- 
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