From 80a6907927461241883a47b552272702978216f8 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 9 Jan 2012 18:08:20 -0600 Subject: ARM: Add support for initparam m5 op --- src/arch/arm/isa/insts/m5ops.isa | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index 3b837cba9..f20908d4f 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -191,16 +191,18 @@ let {{ initparamCode = ''' #if FULL_SYSTEM - Rt = PseudoInst::initParam(xc->tcBase()); + uint64_t ip_val = PseudoInst::initParam(xc->tcBase()); + R0 = bits(ip_val, 31, 0); + R1 = bits(ip_val, 63, 32); #else PseudoInst::panicFsOnlyPseudoInst("initparam"); - Rt = 0; #endif ''' initparamIop = InstObjParams("initparam", "Initparam", "PredOp", { "code": initparamCode, - "predicate_test": predicateTest }) + "predicate_test": predicateTest }, + ["IsNonSpeculative"]) header_output += BasicDeclare.subst(initparamIop) decoder_output += BasicConstructor.subst(initparamIop) exec_output += PredOpExecute.subst(initparamIop) -- cgit v1.2.3 From acbc03ae464b027fe93dca3a0bc796ef63f53113 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 9 Jan 2012 20:13:31 -0600 Subject: X86: Add memory fence to I/O instructions --- src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | 8 ++++++++ src/arch/x86/isa/insts/general_purpose/input_output/string_io.py | 8 ++++++++ 2 files changed, 16 insertions(+) (limited to 'src/arch') diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py index c034f8a48..0465b3447 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -42,26 +42,34 @@ microcode = ''' def macroop IN_R_I { .adjust_imm trimImm(8) limm t1, imm, dataSize=asz + mfence ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence }; def macroop IN_R_R { zexti t2, regm, 15, dataSize=8 + mfence ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence }; def macroop OUT_I_R { .adjust_imm trimImm(8) limm t1, imm, dataSize=8 + mfence st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence }; def macroop OUT_R_R { zexti t2, reg, 15, dataSize=8 + mfence st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py index 3c90ee7e7..044e57edc 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py @@ -45,9 +45,11 @@ def macroop INS_M_R { zexti t2, reg, 15, dataSize=8 + mfence ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True st t6, es, [1, t0, rdi] + mfence add rdi, rdi, t3, dataSize=asz }; @@ -63,6 +65,7 @@ def macroop INS_E_M_R { zexti t2, reg, 15, dataSize=8 + mfence topOfLoop: ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True @@ -72,6 +75,7 @@ topOfLoop: add rdi, rdi, t3, dataSize=asz br label("topOfLoop"), flags=(nCEZF,) end: + mfence fault "NoFault" }; @@ -84,9 +88,11 @@ def macroop OUTS_R_M { zexti t2, reg, 15, dataSize=8 + mfence ld t6, ds, [1, t0, rsi] st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence add rsi, rsi, t3, dataSize=asz }; @@ -102,6 +108,7 @@ def macroop OUTS_E_R_M { zexti t2, reg, 15, dataSize=8 + mfence topOfLoop: ld t6, ds, [1, t0, rsi] st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ @@ -111,6 +118,7 @@ topOfLoop: add rsi, rsi, t3, dataSize=asz br label("topOfLoop"), flags=(nCEZF,) end: + mfence fault "NoFault" }; ''' -- cgit v1.2.3 From 7f782a6c793f30bd7feca66791216263b56f8768 Mon Sep 17 00:00:00 2001 From: Deyuan Guo Date: Thu, 12 Jan 2012 09:58:58 -0500 Subject: mips: definition of MIPS64_QNAN in registers.hh --- src/arch/mips/registers.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index dce7858bf..d3cf1650d 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -55,7 +55,7 @@ const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// const uint32_t MIPS32_QNAN = 0x7fbfffff; -const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); +const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); enum FPControlRegNums { FLOATREG_FIR = NumFloatArchRegs, -- cgit v1.2.3 From a40ec5671fa023ad09de902028bd9e9ca1f1d7da Mon Sep 17 00:00:00 2001 From: Deyuan Guo Date: Thu, 12 Jan 2012 09:58:59 -0500 Subject: mips: Fix decoder of two float-convert instructions --- src/arch/mips/isa/decoder.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 179e409dd..8ebfa66bf 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -1253,7 +1253,7 @@ decode OPCODE_HI default Unknown::unknown() { //When rs=L1 //Note: "1. Format type L is legal only if 64-bit //floating point operations are enabled." - 0x5: decode FUNCTION_HI { + 0x5: decode FUNCTION { format FloatConvertOp { 0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle); 0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble); -- cgit v1.2.3 From 31b6941a52f859cf11c3f35ec4c0ac2f2f11eb14 Mon Sep 17 00:00:00 2001 From: Deyuan Guo Date: Thu, 12 Jan 2012 09:59:00 -0500 Subject: mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FS --- src/arch/mips/faults.cc | 4 +++- src/arch/mips/faults.hh | 14 +++++++++----- src/arch/mips/tlb.cc | 12 +++++++----- 3 files changed, 19 insertions(+), 11 deletions(-) (limited to 'src/arch') diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 9ec93f3fe..00471aece 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -29,6 +29,8 @@ * Authors: Gabe Black * Korey Sewell * Jaidev Patwardhan + * Zhengxing Li + * Deyuan Guo */ #include "arch/mips/faults.hh" @@ -121,7 +123,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) DPRINTF(MipsPRA, "PC: %s\n", pc); bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc(); tc->setMiscRegNoEffect(MISCREG_EPC, - pc.pc() - delay_slot ? sizeof(MachInst) : 0); + pc.pc() - (delay_slot ? sizeof(MachInst) : 0)); // Set Cause_EXCCODE field CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index 89b6924c6..76d4fff23 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -29,6 +29,8 @@ * Authors: Gabe Black * Korey Sewell * Jaidev Patwardhan + * Zhengxing Li + * Deyuan Guo */ #ifndef __MIPS_FAULTS_HH__ @@ -87,7 +89,7 @@ class MipsFaultBase : public FaultBase virtual FaultVect base(ThreadContext *tc) const { StatusReg status = tc->readMiscReg(MISCREG_STATUS); - if (status.bev) + if (!status.bev) return tc->readMiscReg(MISCREG_EBASE); else return 0xbfc00200; @@ -166,7 +168,7 @@ class CoprocessorUnusableFault : public MipsFault if (FULL_SYSTEM) { CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); cause.ce = coProcID; - tc->setMiscReg(MISCREG_CAUSE, cause); + tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); } } }; @@ -178,7 +180,8 @@ class InterruptFault : public MipsFault offset(ThreadContext *tc) const { CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); - return cause.iv ? 0x200 : 0x000; + // offset 0x200 for release 2, 0x180 for release 1. + return cause.iv ? 0x200 : 0x180; } }; @@ -250,9 +253,10 @@ class TlbFault : public AddressFault StaticInstPtr inst = StaticInst::nullStaticInstPtr) { if (FULL_SYSTEM) { - DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); - tc->pcState(this->vect(tc)); + DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name()); + Addr vect = this->vect(tc); setTlbExceptionState(tc, this->code()); + tc->pcState(vect); } else { AddressFault::invoke(tc, inst); } diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 57d8849e1..b3ed09621 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -29,6 +29,8 @@ * Authors: Nathan Binkert * Steve Reinhardt * Jaidev Patwardhan + * Zhengxing Li + * Deyuan Guo */ #include @@ -350,7 +352,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) } if (Valid == false) { - return new InvalidFault(Asid, vaddr, vpn, false); + return new TlbInvalidFault(Asid, vaddr, VPN, false); } else { // Ok, this is really a match, set paddr Addr PAddr; @@ -366,7 +368,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) } } else { // Didn't find any match, return a TLB Refill Exception - return new RefillFault(Asid, vaddr, vpn, false); + return new TlbRefillFault(Asid, vaddr, VPN, false); } } return checkCacheability(req); @@ -445,10 +447,10 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) } if (Valid == false) { - return new InvalidFault(Asid, vaddr, VPN, true); + return new TlbInvalidFault(Asid, vaddr, VPN, write); } else { // Ok, this is really a match, set paddr - if (!Dirty) { + if (!Dirty && write) { return new TlbModifiedFault(Asid, vaddr, VPN); } Addr PAddr; @@ -464,7 +466,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) } } else { // Didn't find any match, return a TLB Refill Exception - return new RefillFault(Asid, vaddr, VPN, true); + return new TlbRefillFault(Asid, vaddr, VPN, write); } } return checkCacheability(req); -- cgit v1.2.3 From 4a59cf00b4b03b63e30a89f1b7f27dbd8bca4f3a Mon Sep 17 00:00:00 2001 From: Deyuan Guo Date: Thu, 12 Jan 2012 09:59:01 -0500 Subject: mips: compatibility between MIPS_SE and cross compiler from CodeSorcery --- src/arch/mips/linux/process.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 156d4ea05..0982e05cb 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -55,7 +55,7 @@ unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, strcpy(name->sysname, "Linux"); strcpy(name->nodename,"m5.eecs.umich.edu"); - strcpy(name->release, "2.4.20"); + strcpy(name->release, "2.6.35"); strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "mips"); -- cgit v1.2.3