From dc2e887f238d48f15364d9937bc71940d3849c0a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 18 Oct 2007 22:39:00 -0700 Subject: X86: Implement the in/out instructions. These will still need support from the TLB and memory system. --HG-- extra : convert_revision : a9503248ea9efca7e5247e4f2830967f428b8215 --- src/arch/x86/isa/decoder/one_byte_opcodes.isa | 16 +++++------ .../general_purpose/input_output/general_io.py | 32 +++++++++++++++++----- src/arch/x86/isa/macroop.isa | 22 ++++++++++++++- src/arch/x86/isa/microasm.isa | 9 ++++-- src/arch/x86/x86_traits.hh | 1 + 5 files changed, 62 insertions(+), 18 deletions(-) (limited to 'src/arch') diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index 6e7fdea35..29b952cab 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -476,10 +476,10 @@ 0x1: Inst::LOOPE(Jb); 0x2: Inst::LOOP(Jb); 0x3: Inst::JRCX(Jb); - 0x4: in_Al_Ib(); - 0x5: in_eAX_Ib(); - 0x6: out_Ib_Al(); - 0x7: out_Ib_eAX(); + 0x4: Inst::IN(rAb,Ib); + 0x5: Inst::IN(rAv,Iv); + 0x6: Inst::OUT(Ib,rAb); + 0x7: Inst::OUT(Iv,rAv); } 0x1D: decode OPCODE_OP_BOTTOM3 { 0x0: Inst::CALL_NEAR(Jz); @@ -489,10 +489,10 @@ default: jmp_far_Ap(); } 0x3: Inst::JMP(Jb); - 0x4: in_Al_Dx(); - 0x5: in_eAX_Dx(); - 0x6: out_Dx_Al(); - 0x7: out_Dx_eAX(); + 0x4: Inst::IN(rAb,rD); + 0x5: Inst::IN(rAv,rD); + 0x6: Inst::OUT(rD,rAb); + 0x7: Inst::OUT(rD,rAv); } 0x1E: decode OPCODE_OP_BOTTOM3 { 0x0: M5InternalError::error( diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py index f9aa9d6e4..c01a11035 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -53,10 +53,28 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class IN(Inst): -# "GenFault ${new UnimpInstFault}" -# class OUT(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' + def macroop IN_R_I { + .adjust_imm trimImm(8) + limm t1, "IntAddrPrefixIO" + ld reg, intseg, [1, t1, t0], imm, addressSize=2 + }; + + def macroop IN_R_R { + limm t1, "IntAddrPrefixIO" + zext t2, regm, 16, dataSize=2 + ld reg, intseg, [1, t1, t2], addressSize=8 + }; + + def macroop OUT_I_R { + .adjust_imm trimImm(8) + limm t1, "IntAddrPrefixIO" + st reg, intseg, [1, t1, t0], imm, addressSize=8 + }; + + def macroop OUT_R_R { + limm t1, "IntAddrPrefixIO" + zext t2, reg, 16, dataSize=2 + st regm, intseg, [1, t1, t2], addressSize=8 + }; +''' diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index c9c33f981..4818b926c 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -142,6 +142,8 @@ def template MacroConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { %(adjust_env)s; + %(adjust_imm)s; + %(adjust_disp)s; %(do_modrm)s; %(constructor)s; //alloc_microops is the code that sets up the microops @@ -159,14 +161,30 @@ let {{ self.microops.append(microop) def setAdjustEnv(self, val): self.adjust_env = val + def adjustImm(self, val): + self.adjust_imm += val + def adjustDisp(self, val): + self.adjust_disp += val def __init__(self, name): super(X86Macroop, self).__init__(name) self.directives = { - "adjust_env" : self.setAdjustEnv + "adjust_env" : self.setAdjustEnv, + "adjust_imm" : self.adjustImm, + "adjust_disp" : self.adjustDisp } self.declared = False self.adjust_env = "" self.doModRM = "" + self.adjust_imm = ''' + uint64_t adjustedImm = IMMEDIATE; + //This is to pacify gcc in case the immediate isn't used. + adjustedImm = adjustedImm; + ''' + self.adjust_disp = ''' + uint64_t adjustedDisp = DISPLACEMENT; + //This is to pacify gcc in case the displacement isn't used. + adjustedDisp = adjustedDisp; + ''' def getAllocator(self, env): return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) def getDeclaration(self): @@ -198,6 +216,8 @@ let {{ {"code" : "", "num_microops" : numMicroops, "alloc_microops" : allocMicroops, "adjust_env" : self.adjust_env, + "adjust_imm" : self.adjust_imm, + "adjust_disp" : self.adjust_disp, "do_modrm" : self.doModRM}) return MacroConstructor.subst(iop); }}; diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 50135e30c..0c43d4c13 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -88,8 +88,8 @@ let {{ "regm" : "env.regm", "xmmlm" : "FLOATREG_XMM_LOW(env.regm)", "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)", - "imm" : "IMMEDIATE", - "disp" : "DISPLACEMENT", + "imm" : "adjustedImm", + "disp" : "adjustedDisp", "seg" : "env.seg", "scale" : "env.scale", "index" : "env.index", @@ -135,6 +135,11 @@ let {{ env.dataSize = 8; ''' + def trimImm(width): + return "adjustedImm = adjustedImm & mask(%s);" % width + + assembler.symbols["trimImm"] = trimImm + def labeler(labelStr): return "label_%s" % labelStr diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index beb1898ce..dd9258db0 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -86,6 +86,7 @@ namespace X86ISA const Addr IntAddrPrefixMask = ULL(0xffffffff00000000); const Addr IntAddrPrefixCPUID = ULL(0x100000000); const Addr IntAddrPrefixMSR = ULL(0x200000000); + const Addr IntAddrPrefixIO = ULL(0x300000000); } #endif //__ARCH_X86_X86TRAITS_HH__ -- cgit v1.2.3