From af6aaf258171027af8d3cf0ef86dddff501a3ccb Mon Sep 17 00:00:00 2001 From: Geoffrey Blake Date: Tue, 31 Jan 2012 07:46:03 -0800 Subject: CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification. --- src/arch/arm/isa.cc | 53 +++++++++++++++++++++++++++++++++++++++- src/arch/arm/isa/insts/m5ops.isa | 4 +-- src/arch/arm/isa/insts/misc.isa | 8 +++--- src/arch/arm/table_walker.cc | 25 ++++++++++++++++--- src/arch/arm/table_walker.hh | 5 +++- src/arch/arm/tlb.cc | 21 ++++++++++++++-- src/arch/arm/tlb.hh | 9 ++++++- src/arch/arm/utility.cc | 5 ++++ 8 files changed, 117 insertions(+), 13 deletions(-) (limited to 'src/arch') diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index b504550a1..5c2478946 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2011 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -39,12 +39,17 @@ */ #include "arch/arm/isa.hh" +#include "config/use_checker.hh" #include "debug/Arm.hh" #include "debug/MiscRegs.hh" #include "sim/faults.hh" #include "sim/stat_control.hh" #include "sim/system.hh" +#if USE_CHECKER +#include "cpu/checker/cpu.hh" +#endif + namespace ArmISA { @@ -279,7 +284,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) PCState pc = tc->pcState(); pc.nextThumb(cpsr.t); pc.nextJazelle(cpsr.j); +#if USE_CHECKER + tc->pcStateNoRecord(pc); +#else tc->pcState(pc); +#endif //USE_CHECKER } else if (misc_reg >= MISCREG_CP15_UNIMP_START && misc_reg < MISCREG_CP15_END) { panic("Unimplemented CP15 register %s wrote with %#x.\n", @@ -382,6 +391,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) oc = sys->getThreadContext(x); oc->getDTBPtr()->allCpusCaching(); oc->getITBPtr()->allCpusCaching(); +#if USE_CHECKER + CheckerCPU *checker = + dynamic_cast(oc->getCheckerCpuPtr()); + if (checker) { + checker->getDTBPtr()->allCpusCaching(); + checker->getITBPtr()->allCpusCaching(); + } +#endif } return; } @@ -399,6 +416,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) assert(oc->getITBPtr() && oc->getDTBPtr()); oc->getITBPtr()->flushAll(); oc->getDTBPtr()->flushAll(); +#if USE_CHECKER + CheckerCPU *checker = + dynamic_cast(oc->getCheckerCpuPtr()); + if (checker) { + checker->getITBPtr()->flushAll(); + checker->getDTBPtr()->flushAll(); + } +#endif } return; case MISCREG_ITLBIALL: @@ -417,6 +442,16 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) bits(newVal, 7,0)); oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), bits(newVal, 7,0)); +#if USE_CHECKER + CheckerCPU *checker = + dynamic_cast(oc->getCheckerCpuPtr()); + if (checker) { + checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), + bits(newVal, 7,0)); + checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), + bits(newVal, 7,0)); + } +#endif } return; case MISCREG_TLBIASIDIS: @@ -427,6 +462,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) assert(oc->getITBPtr() && oc->getDTBPtr()); oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); +#if USE_CHECKER + CheckerCPU *checker = + dynamic_cast(oc->getCheckerCpuPtr()); + if (checker) { + checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); + checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); + } +#endif } return; case MISCREG_TLBIMVAAIS: @@ -437,6 +480,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) assert(oc->getITBPtr() && oc->getDTBPtr()); oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); +#if USE_CHECKER + CheckerCPU *checker = + dynamic_cast(oc->getCheckerCpuPtr()); + if (checker) { + checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); + checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); + } +#endif } return; case MISCREG_ITLBIMVA: diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index f20908d4f..222ecc647 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -247,7 +247,7 @@ let {{ m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", { "code": m5checkpoint_code, "predicate_test": predicateTest }, - ["IsNonSpeculative"]) + ["IsNonSpeculative", "IsUnverifiable"]) header_output += BasicDeclare.subst(m5checkpointIop) decoder_output += BasicConstructor.subst(m5checkpointIop) exec_output += PredOpExecute.subst(m5checkpointIop) @@ -260,7 +260,7 @@ let {{ m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", { "code": m5readfileCode, "predicate_test": predicateTest }, - ["IsNonSpeculative"]) + ["IsNonSpeculative", "IsUnverifiable"]) header_output += BasicDeclare.subst(m5readfileIop) decoder_output += BasicConstructor.subst(m5readfileIop) exec_output += PredOpExecute.subst(m5readfileIop) diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 870f037d0..45d5d8d32 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -525,7 +525,8 @@ let {{ { "code" : wfeCode, "pred_fixup" : wfePredFixUpCode, "predicate_test" : predicateTest }, - ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) + ["IsNonSpeculative", "IsQuiesce", + "IsSerializeAfter", "IsUnverifiable"]) header_output += BasicDeclare.subst(wfeIop) decoder_output += BasicConstructor.subst(wfeIop) exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) @@ -542,7 +543,8 @@ let {{ ''' wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ { "code" : wfiCode, "predicate_test" : predicateTest }, - ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) + ["IsNonSpeculative", "IsQuiesce", + "IsSerializeAfter", "IsUnverifiable"]) header_output += BasicDeclare.subst(wfiIop) decoder_output += BasicConstructor.subst(wfiIop) exec_output += QuiescePredOpExecute.subst(wfiIop) @@ -565,7 +567,7 @@ let {{ ''' sevIop = InstObjParams("sev", "SevInst", "PredOp", \ { "code" : sevCode, "predicate_test" : predicateTest }, - ["IsNonSpeculative", "IsSquashAfter"]) + ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) header_output += BasicDeclare.subst(sevIop) decoder_output += BasicConstructor.subst(sevIop) exec_output += PredOpExecute.subst(sevIop) diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index b2ab010c0..9c92ebdf6 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -107,8 +107,9 @@ TableWalker::getPort(const std::string &if_name, int idx) Fault TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, - TLB::Translation *_trans, bool _timing) + TLB::Translation *_trans, bool _timing, bool _functional) { + assert(!(_functional && _timing)); if (!currState) { // For atomic mode, a new WalkerState instance should be only created // once per TLB. For timing mode, a new instance is generated for every @@ -136,6 +137,7 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _ currState->fault = NoFault; currState->contextId = _cid; currState->timing = _timing; + currState->functional = _functional; currState->mode = _mode; /** @todo These should be cached or grabbed from cached copies in @@ -230,12 +232,21 @@ TableWalker::processWalk() stateQueueL1.size()); stateQueueL1.push_back(currState); currState = NULL; - } else { + } else if (!currState->functional) { port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), NULL, (uint8_t*)&currState->l1Desc.data, currState->tc->getCpuPtr()->ticks(1), flag); doL1Descriptor(); f = currState->fault; + } else { + RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag); + PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); + pkt->dataStatic((uint8_t*)&currState->l1Desc.data); + port->sendFunctional(pkt); + doL1Descriptor(); + delete req; + delete pkt; + f = currState->fault; } return f; @@ -566,11 +577,19 @@ TableWalker::doL1Descriptor() port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, currState->tc->getCpuPtr()->ticks(1)); - } else { + } else if (!currState->functional) { port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), NULL, (uint8_t*)&currState->l2Desc.data, currState->tc->getCpuPtr()->ticks(1)); doL2Descriptor(); + } else { + RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0); + PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); + pkt->dataStatic((uint8_t*)&currState->l2Desc.data); + port->sendFunctional(pkt); + doL2Descriptor(); + delete req; + delete pkt; } return; default: diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 85db1fa77..d4a2e87b5 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -294,6 +294,9 @@ class TableWalker : public MemObject /** If the mode is timing or atomic */ bool timing; + /** If the atomic mode should be functional */ + bool functional; + /** Save mode for use in delayed response */ BaseTLB::Mode mode; @@ -354,7 +357,7 @@ class TableWalker : public MemObject virtual Port *getPort(const std::string &if_name, int idx = -1); Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, - TLB::Translation *_trans, bool timing); + TLB::Translation *_trans, bool timing, bool functional = false); void setTlb(TLB *_tlb) { tlb = _tlb; } void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index a03e445cf..f4dc47655 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -453,8 +453,11 @@ TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, Fault TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, - Translation *translation, bool &delay, bool timing) + Translation *translation, bool &delay, bool timing, bool functional) { + // No such thing as a functional timing access + assert(!(timing && functional)); + if (!miscRegValid) { updateMiscReg(tc); DPRINTF(TLBVerbose, "TLB variables changed!\n"); @@ -541,7 +544,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", vaddr, contextId); fault = tableWalker->walk(req, tc, contextId, mode, translation, - timing); + timing, functional); if (timing && fault == NoFault) { delay = true; // for timing mode, return and wait for table walk @@ -700,6 +703,20 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) return fault; } +Fault +TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) +{ + bool delay = false; + Fault fault; +#if FULL_SYSTEM + fault = translateFs(req, tc, mode, NULL, delay, false, true); +#else + fault = translateSe(req, tc, mode, NULL, delay, false); +#endif + assert(!delay); + return fault; +} + Fault TLB::translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode) diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 3464e42b3..bdfa2fc9f 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -182,6 +182,12 @@ class TLB : public BaseTLB */ bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); + /** + * Do a functional lookup on the TLB (for checker cpu) that + * behaves like a normal lookup without modifying any page table state. + */ + Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); + /** Accessor functions for memory attributes for last accessed TLB entry */ void @@ -197,7 +203,8 @@ class TLB : public BaseTLB #if FULL_SYSTEM Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, - Translation *translation, bool &delay, bool timing); + Translation *translation, bool &delay, + bool timing, bool functional = false); #else Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing); diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 98195ab04..b31dc4324 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -41,6 +41,7 @@ #include "arch/arm/faults.hh" #include "arch/arm/isa_traits.hh" #include "arch/arm/utility.hh" +#include "config/use_checker.hh" #include "cpu/thread_context.hh" #if FULL_SYSTEM @@ -116,7 +117,11 @@ skipFunction(ThreadContext *tc) { TheISA::PCState newPC = tc->pcState(); newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); +#if USE_CHECKER + tc->pcStateNoRecord(newPC); +#else tc->pcState(newPC); +#endif } void -- cgit v1.2.3 From 0ed3c84c7b05d7d3c9d5f0e3f1c05c20afef93b9 Mon Sep 17 00:00:00 2001 From: Dam Sunwoo Date: Tue, 31 Jan 2012 07:46:04 -0800 Subject: util: implements "writefile" gem5 op to export file from guest to host filesystem Usage: m5 writefile File will be created in the gem5 output folder with the identical filename. Implementation is largely based on the existing "readfile" functionality. Currently does not support exporting of folders. --- src/arch/arm/isa/formats/m5ops.isa | 1 + src/arch/arm/isa/insts/m5ops.isa | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) (limited to 'src/arch') diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa index f532d828b..534d12cd9 100644 --- a/src/arch/arm/isa/formats/m5ops.isa +++ b/src/arch/arm/isa/formats/m5ops.isa @@ -64,6 +64,7 @@ def format M5ops() {{ case 0x42: return new Dumpresetstats(machInst); case 0x43: return new M5checkpoint(machInst); #if FULL_SYSTEM + case 0x4F: return new M5writefile(machInst); case 0x50: return new M5readfile(machInst); #endif case 0x51: return new M5break(machInst); diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index 222ecc647..1a154459e 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -265,6 +265,24 @@ let {{ decoder_output += BasicConstructor.subst(m5readfileIop) exec_output += PredOpExecute.subst(m5readfileIop) + m5writefileCode = ''' +#if FULL_SYSTEM + int n = 4; + uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); + n = 6; + Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false); + R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset, + filenameAddr); +#endif + ''' + m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp", + { "code": m5writefileCode, + "predicate_test": predicateTest }, + ["IsNonSpeculative"]) + header_output += BasicDeclare.subst(m5writefileIop) + decoder_output += BasicConstructor.subst(m5writefileIop) + exec_output += PredOpExecute.subst(m5writefileIop) + m5breakIop = InstObjParams("m5break", "M5break", "PredOp", { "code": "PseudoInst::debugbreak(xc->tcBase());", "predicate_test": predicateTest }, -- cgit v1.2.3 From 7d4f18770073d968c70cd3ffcdd117f50a6056a2 Mon Sep 17 00:00:00 2001 From: Koan-Sin Tan Date: Tue, 31 Jan 2012 12:05:52 -0500 Subject: clang: Enable compiling gem5 using clang 2.9 and 3.0 This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places. --- src/arch/alpha/tlb.cc | 4 ++-- src/arch/alpha/tlb.hh | 2 +- src/arch/arm/insts/static_inst.hh | 1 + src/arch/arm/insts/vfp.hh | 3 +++ src/arch/arm/isa/templates/basic.isa | 2 +- src/arch/arm/miscregs.cc | 2 +- src/arch/generic/memhelpers.hh | 4 ++-- src/arch/mips/faults.cc | 2 +- src/arch/mips/faults.hh | 2 +- src/arch/x86/bios/acpi.hh | 8 ++++---- src/arch/x86/bios/intelmp.cc | 2 +- src/arch/x86/bios/intelmp.hh | 24 ++++++++++++------------ src/arch/x86/bios/smbios.hh | 6 +++--- 13 files changed, 33 insertions(+), 29 deletions(-) (limited to 'src/arch') diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index b211c4923..26d290a50 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -63,7 +63,7 @@ TLB::TLB(const Params *p) : BaseTLB(p), size(p->size), nlu(0) { table = new TlbEntry[size]; - memset(table, 0, sizeof(TlbEntry[size])); + memset(table, 0, sizeof(TlbEntry) * size); flushCache(); } @@ -279,7 +279,7 @@ void TLB::flushAll() { DPRINTF(TLB, "flushAll\n"); - memset(table, 0, sizeof(TlbEntry[size])); + memset(table, 0, sizeof(TlbEntry) * size); flushCache(); lookupTable.clear(); nlu = 0; diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index b6261769f..1d4b6c6f8 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -49,7 +49,7 @@ class ThreadContext; namespace AlphaISA { -class TlbEntry; +struct TlbEntry; class TLB : public BaseTLB { diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index fa850190f..5af97b796 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -46,6 +46,7 @@ #include "arch/arm/utility.hh" #include "base/trace.hh" #include "cpu/static_inst.hh" +#include "sim/byteswap.hh" namespace ArmISA { diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh index 57b74d040..b3582a351 100644 --- a/src/arch/arm/insts/vfp.hh +++ b/src/arch/arm/insts/vfp.hh @@ -107,6 +107,9 @@ enum VfpRoundingMode VfpRoundZero = 3 }; +static inline float bitsToFp(uint64_t, float); +static inline uint32_t fpToBits(float); + template static inline bool flushToZero(fpType &op) diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa index 0728b66e3..b3878b89a 100644 --- a/src/arch/arm/isa/templates/basic.isa +++ b/src/arch/arm/isa/templates/basic.isa @@ -49,7 +49,7 @@ def template BasicDeclare {{ // Basic instruction class constructor template. def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index db097c653..c31818377 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -411,7 +411,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) } break; case 11: - if (opc1 >= 0 && opc1 <=7) { + if (opc1 <=7) { switch (crm) { case 0: case 1: diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh index c753aaf2a..f7bbfa269 100644 --- a/src/arch/generic/memhelpers.hh +++ b/src/arch/generic/memhelpers.hh @@ -64,7 +64,7 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, memset(&mem, 0, sizeof(mem)); Fault fault = readMemTiming(xc, traceData, addr, mem, flags); if (fault == NoFault) { - mem = gtoh(mem); + mem = TheISA::gtoh(mem); if (traceData) traceData->setData(mem); } @@ -92,7 +92,7 @@ writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem, { Fault fault = writeMemTiming(xc, traceData, mem, addr, flags, res); if (fault == NoFault && res != NULL) { - *res = gtoh((MemT)*res); + *res = TheISA::gtoh((MemT)*res); } return fault; } diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 00471aece..26b7c7557 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -98,7 +98,7 @@ template <> FaultVals MipsFault::vals = template <> FaultVals MipsFault::vals = { "TLB Refill Exception", 0x180, ExcCodeDummy }; -template <> FaultVals MipsFault::vals = +template <> MipsFaultBase::FaultVals MipsFault::vals = { "TLB Modified Exception", 0x180, ExcCodeMod }; void diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index 76d4fff23..912b42cde 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -299,7 +299,7 @@ class TlbModifiedFault : public TlbFault TlbFault(asid, vaddr, vpn, false) {} - ExcCode code() const { return vals.code; } + ExcCode code() const { return MipsFault::code(); } }; } // namespace MipsISA diff --git a/src/arch/x86/bios/acpi.hh b/src/arch/x86/bios/acpi.hh index 5040c434c..b10b18092 100644 --- a/src/arch/x86/bios/acpi.hh +++ b/src/arch/x86/bios/acpi.hh @@ -48,11 +48,11 @@ class Port; -class X86ACPIRSDPParams; +struct X86ACPIRSDPParams; -class X86ACPISysDescTableParams; -class X86ACPIRSDTParams; -class X86ACPIXSDTParams; +struct X86ACPISysDescTableParams; +struct X86ACPIRSDTParams; +struct X86ACPIXSDTParams; namespace X86ISA { diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc index 974af28a5..4c9c61adb 100644 --- a/src/arch/x86/bios/intelmp.cc +++ b/src/arch/x86/bios/intelmp.cc @@ -72,7 +72,7 @@ template uint8_t writeOutField(PortProxy* proxy, Addr addr, T val) { - T guestVal = X86ISA::htog(val); + uint64_t guestVal = X86ISA::htog(val); proxy->writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T)); uint8_t checkSum = 0; diff --git a/src/arch/x86/bios/intelmp.hh b/src/arch/x86/bios/intelmp.hh index 0ddb62b8d..4b730ad4b 100644 --- a/src/arch/x86/bios/intelmp.hh +++ b/src/arch/x86/bios/intelmp.hh @@ -54,24 +54,24 @@ class PortProxy; // Config entry types -class X86IntelMPBaseConfigEntryParams; -class X86IntelMPExtConfigEntryParams; +struct X86IntelMPBaseConfigEntryParams; +struct X86IntelMPExtConfigEntryParams; // General table structures -class X86IntelMPConfigTableParams; -class X86IntelMPFloatingPointerParams; +struct X86IntelMPConfigTableParams; +struct X86IntelMPFloatingPointerParams; // Base entry types -class X86IntelMPBusParams; -class X86IntelMPIOAPICParams; -class X86IntelMPIOIntAssignmentParams; -class X86IntelMPLocalIntAssignmentParams; -class X86IntelMPProcessorParams; +struct X86IntelMPBusParams; +struct X86IntelMPIOAPICParams; +struct X86IntelMPIOIntAssignmentParams; +struct X86IntelMPLocalIntAssignmentParams; +struct X86IntelMPProcessorParams; // Extended entry types -class X86IntelMPAddrSpaceMappingParams; -class X86IntelMPBusHierarchyParams; -class X86IntelMPCompatAddrSpaceModParams; +struct X86IntelMPAddrSpaceMappingParams; +struct X86IntelMPBusHierarchyParams; +struct X86IntelMPCompatAddrSpaceModParams; namespace X86ISA { diff --git a/src/arch/x86/bios/smbios.hh b/src/arch/x86/bios/smbios.hh index 9fa6cd6dc..805b03fbb 100644 --- a/src/arch/x86/bios/smbios.hh +++ b/src/arch/x86/bios/smbios.hh @@ -52,9 +52,9 @@ #include "sim/sim_object.hh" class PortProxy; -class X86SMBiosBiosInformationParams; -class X86SMBiosSMBiosStructureParams; -class X86SMBiosSMBiosTableParams; +struct X86SMBiosBiosInformationParams; +struct X86SMBiosSMBiosStructureParams; +struct X86SMBiosSMBiosTableParams; namespace X86ISA { -- cgit v1.2.3