From 4e8d2d1593475008b926829e6944a59963166079 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 2 Mar 2007 22:34:51 -0500 Subject: make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42 --- src/base/bigint.hh | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/base/bigint.hh') diff --git a/src/base/bigint.hh b/src/base/bigint.hh index aa60eeb04..d533e662a 100644 --- a/src/base/bigint.hh +++ b/src/base/bigint.hh @@ -42,9 +42,22 @@ struct m5_twin64_t { } }; +struct m5_twin32_t { + uint32_t a; + uint32_t b; + inline m5_twin32_t& operator=(const uint32_t x) + { + a = x; + b = x; + return *this; + } +}; + + // This is for twin loads (two 64 bit values), not 1 128 bit value (as far as // endian conversion is concerned! typedef m5_twin64_t Twin64_t; +typedef m5_twin32_t Twin32_t; #endif // __BASE_BIGINT_HH__ -- cgit v1.2.3