From baba18ab9214d1fe2236cd932c3bfca5ddfb06d6 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 16 Jun 2006 17:08:47 -0400 Subject: Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble. First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model. Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled. SConstruct: Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled. configs/test/test.py: Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick. src/base/traceflags.py: Add in O3CPU trace flag. src/cpu/SConscript: Rename AlphaFullCPU to AlphaO3CPU. Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included. src/cpu/base_dyn_inst.cc: src/cpu/base_dyn_inst.hh: Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU. src/cpu/cpu_models.py: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model. src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: src/cpu/o3/cpu.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/thread_state.hh: src/python/m5/objects/AlphaO3CPU.py: Rename FullCPU to O3CPU to differentiate from old FullCPU model. src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: Rename FullCPU to O3CPU to differentiate from old FullCPU model. Also #ifdef the checker code so it doesn't need to be included if it's not selected. --HG-- rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a --- src/base/traceflags.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/base/traceflags.py') diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 7ff68bcaf..c4dcb695b 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -115,6 +115,7 @@ baseFlags = [ 'MSHR', 'Mbox', 'MemDepUnit', + 'O3CPU', 'OzoneCPU', 'FE', 'IBE', -- cgit v1.2.3 From 23cfd9489bdff00f926f5dcfb7dd72333fb11bfb Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Sat, 1 Jul 2006 19:02:43 -0400 Subject: traceflag stuff src/base/traceflags.py: add BaseCPU flag, O3CPUAll flag grouping src/cpu/base.cc: Use BaseCPU flag instead of FullCPU flag --HG-- extra : convert_revision : 32f737a2f58eb936634799f1f809e07cbba90179 --- src/base/traceflags.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/base/traceflags.py') diff --git a/src/base/traceflags.py b/src/base/traceflags.py index c4dcb695b..d51236c46 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -115,6 +115,7 @@ baseFlags = [ 'MSHR', 'Mbox', 'MemDepUnit', + 'BaseCPU' 'O3CPU', 'OzoneCPU', 'FE', @@ -176,7 +177,7 @@ compoundFlagMap = { 'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], 'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], 'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ], - 'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'Activity','Scoreboard','Writeback'], + 'O3CPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'O3CPU', 'Activity','Scoreboard','Writeback'], 'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU'] } -- cgit v1.2.3 From c8b3d8a1edbab505e5f9748cfa1ee866ed1fb02f Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Sun, 2 Jul 2006 23:11:24 -0400 Subject: Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads) Edit Test3 for newmem src/base/traceflags.py: Add O3CPU flag src/cpu/base.cc: for some reason adding a BaseCPU flag doesnt work so just go back to old way... src/cpu/o3/alpha/cpu_builder.cc: Determine number threads by workload size instead of solely by parameter. Default SMT fetch policy to RoundRobin if it's not specified in Config file src/cpu/o3/commit.hh: only use nextNPC for !ALPHA src/cpu/o3/commit_impl.hh: add FetchTrapPending as condition for commit src/cpu/o3/cpu.cc: panic if active threads is more than Impl::MaxThreads src/cpu/o3/fetch.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: name stuff src/cpu/o3/fetch_impl.hh: fatal if try to use SMT branch count, that's unimplemented right now src/python/m5/config.py: make it clearer that a parameter is not valid within a configuration class --HG-- extra : convert_revision : 55069847304e40e257f9225f0dc3894ce6491b34 --- src/base/traceflags.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/base/traceflags.py') diff --git a/src/base/traceflags.py b/src/base/traceflags.py index d51236c46..327ce6075 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -121,6 +121,7 @@ baseFlags = [ 'FE', 'IBE', 'BE', + 'O3CPU', 'OzoneLSQ', 'PCEvent', 'PCIA', -- cgit v1.2.3 From e41fd9cb6309083c32a2795e3ac449628138d441 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 5 Jul 2006 15:55:45 -0400 Subject: Alphabetize traceflags, rename FullCPUAll flag to O3CPUAll. --HG-- extra : convert_revision : f558966154376223674c82d513afc2dad6591426 --- src/base/traceflags.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/base/traceflags.py') diff --git a/src/base/traceflags.py b/src/base/traceflags.py index c4dcb695b..27c24107c 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -48,8 +48,10 @@ ccfilename = sys.argv[1] + '.cc' # To define a new flag, simply add it to this list. # baseFlags = [ + 'Activity', 'AlphaConsole', 'BADADDR', + 'BE', 'BPredRAS', 'Bus', 'BusAddrRanges', @@ -84,6 +86,7 @@ baseFlags = [ 'EthernetPIO', 'EthernetSM', 'Event', + 'FE', 'Fault', 'Fetch', 'Flow', @@ -97,6 +100,7 @@ baseFlags = [ 'GDBSend', 'GDBWrite', 'HWPrefetch', + 'IBE', 'IEW', 'IIC', 'IICMore', @@ -117,9 +121,6 @@ baseFlags = [ 'MemDepUnit', 'O3CPU', 'OzoneCPU', - 'FE', - 'IBE', - 'BE', 'OzoneLSQ', 'PCEvent', 'PCIA', @@ -133,6 +134,7 @@ baseFlags = [ 'RenameMap', 'SQL', 'Sampler', + 'Scoreboard', 'ScsiCtrl', 'ScsiDisk', 'ScsiNone', @@ -156,8 +158,6 @@ baseFlags = [ 'Uart', 'VtoPhys', 'WriteBarrier', - 'Activity', - 'Scoreboard', 'Writeback', ] @@ -176,7 +176,7 @@ compoundFlagMap = { 'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], 'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], 'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ], - 'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'Activity','Scoreboard','Writeback'], + 'O3CPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'O3CPU', 'Activity','Scoreboard','Writeback'], 'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU'] } -- cgit v1.2.3 From ea9697250cf55add36af1548b524ab22d6a2cf94 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 5 Jul 2006 16:54:24 -0400 Subject: Fix up some merge problems. src/base/traceflags.py: Remove BaseCPU traceflag. src/cpu/o3/alpha/params.hh: Move non-Alpha specific parameters out of this params class. src/cpu/o3/params.hh: Move non-Alpha specific params into this params class. --HG-- extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514 --- src/base/traceflags.py | 1 - 1 file changed, 1 deletion(-) (limited to 'src/base/traceflags.py') diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 9ceba3017..27c24107c 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -51,7 +51,6 @@ baseFlags = [ 'Activity', 'AlphaConsole', 'BADADDR', - 'BaseCPU', 'BE', 'BPredRAS', 'Bus', -- cgit v1.2.3