From 83af0fdcf57175adf8077c51e9ba872dd2c04b76 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 21 Jun 2007 11:59:17 -0700 Subject: Getting closer... configs/example/memtest.py: Add progress interval option. src/base/traceflags.py: Add MemTest flag. src/cpu/memtest/memtest.cc: Clean up tracing. src/cpu/memtest/memtest.hh: Get rid of unused code. --HG-- extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87 --- src/base/traceflags.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/base/traceflags.py') diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 6b241c410..f4cf7dfd7 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -128,6 +128,7 @@ baseFlags = [ 'Mbox', 'MemDepUnit', 'MemoryAccess', + 'MemTest', 'O3CPU', 'OzoneCPU', 'OzoneLSQ', -- cgit v1.2.3 From 15a51d0cae01defc116c9a937bfa8c4577f72826 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 14 Jul 2007 13:28:52 -0700 Subject: Add CacheRepl trace flag and move a couple DPRINTFs to it. --HG-- extra : convert_revision : 31724d19ebdf2cdc2a2bafff83d17845b3a0b183 --- src/base/traceflags.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/base/traceflags.py') diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 70fadb210..8573eb9bf 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -47,6 +47,7 @@ baseFlags = [ 'BusBridge', 'Cache', 'CachePort', + 'CacheRepl', 'Chains', 'Checker', 'Clock', -- cgit v1.2.3