From 9c5373ca61587409e4d0f6ad4c032e8d53be28ca Mon Sep 17 00:00:00 2001 From: Austin Harris Date: Wed, 26 Dec 2018 19:19:00 -0600 Subject: arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power Reviewed-by: Alec Roelke Maintainer: Alec Roelke --- src/base/loader/elf_object.cc | 2 +- src/base/loader/object_file.hh | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/base') diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index 60c79f803..761fd79f5 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -112,7 +112,7 @@ ElfObject::tryFile(const std::string &fname, size_t len, uint8_t *data, ehdr.e_ident[EI_CLASS] == ELFCLASS64) { arch = Arm64; } else if (ehdr.e_machine == EM_RISCV) { - arch = Riscv; + arch = (ehdr.e_ident[EI_CLASS] == ELFCLASS64) ? Riscv64 : Riscv32; } else if (ehdr.e_machine == EM_PPC && ehdr.e_ident[EI_CLASS] == ELFCLASS32) { arch = Power; diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh index c2cdafe47..09c453b8d 100644 --- a/src/base/loader/object_file.hh +++ b/src/base/loader/object_file.hh @@ -57,7 +57,8 @@ class ObjectFile Arm, Thumb, Power, - Riscv + Riscv64, + Riscv32 }; enum OpSys { -- cgit v1.2.3