From 50f1570352a036aed49a078b17fa1af54d0a1787 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 21 Apr 2009 15:40:25 -0700 Subject: arm: Unify the ARM tlb. We forgot about this when we did the rest. This code compiles, but there are no tests still --- src/cpu/BaseCPU.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/BaseCPU.py') diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 3aa9b87bb..4661375ba 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -54,7 +54,7 @@ elif build_env['TARGET_ISA'] == 'mips': if build_env['FULL_SYSTEM']: from MipsInterrupts import MipsInterrupts elif build_env['TARGET_ISA'] == 'arm': - from ArmTLB import ArmDTB + from ArmTLB import ArmTLB if build_env['FULL_SYSTEM']: from ArmInterrupts import ArmInterrupts @@ -109,8 +109,8 @@ class BaseCPU(MemObject): MipsInterrupts(), "Interrupt Controller") elif build_env['TARGET_ISA'] == 'arm': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") - dtb = Param.ArmTLB(ArmDTB(), "Data TLB") - itb = Param.ArmTLB(ArmITB(), "Instruction TLB") + dtb = Param.ArmTLB(ArmTLB(), "Data TLB") + itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") if build_env['FULL_SYSTEM']: interrupts = Param.ArmInterrupts( ArmInterrupts(), "Interrupt Controller") -- cgit v1.2.3