From ab598eadbfeefceb6501d4cca13147b660642d9e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 21 Nov 2007 00:04:15 -0800 Subject: imported patch pagewalker.patch --HG-- extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f --- src/cpu/BaseCPU.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/cpu/BaseCPU.py') diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 691f92e2e..ee5ed0774 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -101,6 +101,8 @@ class BaseCPU(SimObject): tracer = Param.InstTracer(default_tracer, "Instruction tracer") _mem_ports = [] + if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: + _mem_ports = ["itb.walker.port", "dtb.walker.port"] def connectMemPorts(self, bus): for p in self._mem_ports: @@ -108,12 +110,14 @@ class BaseCPU(SimObject): exec('self.%s = bus.port' % p) def addPrivateSplitL1Caches(self, ic, dc): - assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3) + assert(len(self._mem_ports) < 6) self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] + if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: + self._mem_ports += ["itb.walker_port", "dtb.walker_port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) -- cgit v1.2.3