From 2012202b06a620998709f605f8f8692ad718294d Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Tue, 12 May 2009 15:01:14 -0400 Subject: inorder/alpha-isa: create eaComp object visible to StaticInst through ISA Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * * --- src/cpu/SConscript | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu/SConscript') diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 344deb9cf..854db9f12 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -49,6 +49,8 @@ execfile(models_db.srcnode().abspath) # Template for execute() signature. exec_sig_template = ''' virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; +virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const +{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const { panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; virtual Fault completeAcc(Packet *pkt, %(type)s *xc, @@ -59,6 +61,8 @@ virtual int memAccSize(%(type)s *xc) ''' mem_ini_sig_template = ''' +virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const +{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; ''' -- cgit v1.2.3