From 8dd7700482b8ad7fa5e96469b23f0c917f5e3599 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 28 Jul 2007 20:30:43 -0700
Subject: Turn the instruction tracing code into pluggable sim objects. These
 need to be refined a little still and given parameters.

--HG--
extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
---
 src/cpu/SConscript | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'src/cpu/SConscript')

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index adf47fa4d..b686c0d95 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -105,12 +105,15 @@ CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
 
 SimObject('BaseCPU.py')
 SimObject('FuncUnit.py')
+SimObject('ExeTracer.py')
+SimObject('IntelTrace.py')
 
 Source('activity.cc')
 Source('base.cc')
 Source('cpuevent.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
+Source('inteltrace.cc')
 Source('pc_event.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')
@@ -123,6 +126,14 @@ if env['FULL_SYSTEM']:
     Source('intr_control.cc')
     Source('profile.cc')
 
+    if env['TARGET_ISA'] == 'sparc':
+        SimObject('LegionTrace.py')
+        Source('legiontrace.cc')
+
+if env['TARGET_ISA'] == 'x86':
+    SimObject('NativeTrace.py')
+    Source('nativetrace.cc')
+
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
     checker_supports = False
-- 
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