From 166da650a3c864b31193ade893ed99e547c67644 Mon Sep 17 00:00:00 2001 From: Rekai Gonzalez-Alberquilla Date: Wed, 5 Apr 2017 13:24:23 -0500 Subject: arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez Maintainer: Andreas Sandberg --- src/cpu/StaticInstFlags.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/cpu/StaticInstFlags.py') diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py index ef29726fc..55ef456ce 100644 --- a/src/cpu/StaticInstFlags.py +++ b/src/cpu/StaticInstFlags.py @@ -58,6 +58,8 @@ class StaticInstFlags(Enum): 'IsInteger', # References integer regs. 'IsFloating', # References FP regs. 'IsCC', # References CC regs. + 'IsVector', # References Vector regs. + 'IsVectorElem', # References Vector reg elems. 'IsMemRef', # References memory (load, store, or prefetch) 'IsLoad', # Reads from memory (load or prefetch). -- cgit v1.2.3